Datasheet > LTC4270

LTC4270

更新时间： 2023-12-20 18:44:10

品牌	Logo	应用领域
亚德诺 - ADI		控制器
页数	文件大小	规格书
32页	1522K
描述
12 端口 PoE / PoE+ / LTPoE++ PSE 控制器

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LTC4270 数据手册

LTC4270/LTC4271

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. AGND – V_EE= 54V and V_DD– DGND = 3.3V unless otherwise noted.

(Notes 3 & 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I C Timing

Clock Frequency

(Note 7)

MHz

µs

SCLK

Bus Free Time

Figure 5 (Notes 7, 9)

(Notes 7, 9, 10)

480

240

480

240

Start Hold Time

SCL Low Time

SCL High Time

SDAIN Data Hold Time

Data Clock to SDAOUT Valid

Data Set-Up Time

130

Start Set-Up Time

240

Stop Set-Up Time

SCL, SDAIN Rise Time

SCL, SDAIN Fall Time

Fault Present to INT Pin Low

Stop Condition to INT Pin Low

ARA to INT Pin High Time

SCL Fall to ACK Low

120

150

1.5

130

(Notes 7, 9, 10)

(Notes 7, 9)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. With the exception of (V

DGND), exposure to any Absolute Maximum Rating condition for extended

periods may affect device reliability and lifetime.

Note 7: Guaranteed by design, not subject to test.

Note 8: The IEEE 802.3af specification allows a PD to present its

Maintain Power Signature (MPS) on an intermittent basis without being

disconnected. In order to stay powered, the PD must present the MPS for

–

Note 2: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 140ºC when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: All currents into device pins are positive; all currents out of device

pins are negative.

Note 4: The LTC4270 operates with a negative supply voltage (with

respect to AGND). To avoid confusion, voltages in this data sheet are

referred to in terms of absolute magnitude.

within any t

time window.

MPS

MPDO

Note 9: Values Measured at V and V

Note 10: If a fault condition occurs during an I C transaction, the INT pin

will not be pulled down until a stop condition is present on the I C bus.

Note 11: Load characteristics of the LTC4270 during Mark: 7V < (AGND –

ILD

IHD

) < 10V or I

OUTn

< 50µA.

OUT

Note 12: See the LTC4271 Software Programming documentation for

information on serial bus usage and device configuration and status

registers.

Note 13: Do not source or sink current from CAP1 and CAP2.

Note 5: t is the same as t

defined by IEEE 802.3at

DIS

MPDO

Note 6: The LTC4271 digital interface operates with respect to DGND. All

logic levels are measured with respect to DGND.

Rev E

For more information www.analog.com

1...4 5 678 9 10...32

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与LTC4270相关器件

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LTC4270/	Linear	获取价格	8-Port PoE/PoE PSE Controller
LTC4270_12	Linear	获取价格	12-Port PoE/PoE+/LTPoE++ PSE Controller
LTC4270_15	Linear	获取价格	12-Port PoE/PoE/LTPoE PSE Controller
LTC4270AIUKG#PBF	Linear	获取价格	LTC4270/LTC4271 - 12-Port PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 52; Tempera
LTC4270BIUKG#PBF	Linear	获取价格	暂无描述
LTC4270CIUKG#PBF	Linear	获取价格	LTC4270/LTC4271 - 12-Port PoE/PoE+/LTPoE++ PSE Controller; Package: QFN; Pins: 52; Tempera
LTC4271	Linear	获取价格	Quad PoE/PoE/LTPoE PSE Controller
LTC4271	ADI	获取价格	PoE/PoE+/LTPoE++ PSE数字控制器
LTC4271_15	Linear	获取价格	12-Port PoE/PoE/LTPoE PSE Controller
LTC4271IUF#PBF	Linear	获取价格	暂无描述

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