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LTC4150IMS#TR PDF预览

LTC4150IMS#TR

更新时间： 2024-01-24 02:13:03
品牌 Logo 应用领域
凌特 - Linear 电池仪表光电二极管
页数 文件大小 规格书
14页 161K
描述
LTC4150 - Coulomb Counter/Battery Gas Gauge; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C

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LTC4150IMS#TR 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：MSOP包装说明：TSSOP, TSSOP10,.19,20
针数：10Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.05模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：S-PDSO-G10JESD-609代码：e0
长度：3 mm湿度敏感等级：1
功能数量：1端子数量：10
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP10,.19,20封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：235
电源：2.7/8.5 V认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Power Management Circuits
最大供电电流 (Isup)：0.14 mA最大供电电压 (Vsup)：8.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：4 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：3 mmBase Number Matches：1

LTC4150IMS#TR 数据手册

 浏览型号LTC4150IMS#TR的Datasheet PDF文件第6页浏览型号LTC4150IMS#TR的Datasheet PDF文件第7页浏览型号LTC4150IMS#TR的Datasheet PDF文件第8页浏览型号LTC4150IMS#TR的Datasheet PDF文件第10页浏览型号LTC4150IMS#TR的Datasheet PDF文件第11页浏览型号LTC4150IMS#TR的Datasheet PDF文件第12页 
LTC4150  
APPLICATIONS INFORMATION  
INT, POL and CLR  
Interfacing to INT, POL, CLR and SHDN  
INT asserts low each time the LTC4150 measures a unit  
of charge. At the same time, POL is latched to indicate  
the polarity of the charge unit. The integrator and counter  
continuerunning,sothemicrocontrollermustserviceand  
clear the interrupt before another unit of charge accumu-  
lates. Otherwise, one measurement will be lost. The time  
available between interrupts is the reciprocal of  
The LTC4150 operates directly from the battery, while in  
most cases the microcontroller supply comes from some  
separate, regulatedsource. ThisposesnoproblemforINT  
and POL because they are open-drain outputs and can  
be pulled up to any voltage 9V or less, regardless of the  
voltage applied to the LTC4150’s V .  
DD  
CLR and SHDN inputs require special attention. To drive  
them, the microcontroller or external logic must generate  
a minimum logic high level of 1.9V. The maximum input  
Equation 2:  
1
GVF •⏐VSENSE  
level for these pins is V + 0.3V. If the microcontroller’s  
Time per INT Assertion =  
(9)  
DD  
⏐
supply is more than this, resistive dividers must be used  
on CLR and SHDN. The schematic in Figure 6 shows an  
At 50mV full scale, the minimum time available is 596ms.  
To be conservative and accommodate for small, unex-  
pectedexcursionsabovethe50mVsensevoltagelimit,the  
microcontroller should process the interrupt and polarity  
information and clear INT within 500ms.  
application with INT driving CLR and microcontroller V  
CC  
> V . The resistive dividers on CLR and SHDN keep the  
DD  
voltages at these pins within the LTC4150’s V range.  
DD  
Choose R2 and R1 so that:  
(R1 + R2) ≥ 50R  
(12)  
(13)  
L
Toggling CLR low for at least 20μs resets INT high and  
unlatchesPOL.SincetheLTC4150’sintegratorandcounter  
operate independently of the INT and POL latches, no  
charge information is lost during the latched period or  
while CLR is low. Charge/discharge information contin-  
ues to accumulate during those intervals and accuracy  
is unaffected.  
R1  
1.9V ≤  
VCC ≤ VDD (Minimum)  
R1+R2  
Equation 13 also applies to the selection of R3 and R4.  
The minimum V is the lowest supply to the LTC4150  
DD  
when the battery powering it is at its lowest discharged  
voltage.  
Once cleared, INT idles in a high state and POL indicates  
real-timepolarityofthebatterycurrent.POLhighindicates  
charge flowing into the battery and low indicates charge  
flowing out. Indication of a polarity change requires at  
least:  
When the battery is removed in any application, the CLR  
and SHDN inputs are unpredictable. INT and POL outputs  
may be erratic and should be ignored until after the bat-  
tery is replaced.  
If desired, the simple logic of Figure 4 may be used to  
derive separate charge and discharge pulse trains from  
INT and POL.  
2
tPOL  
=
(10)  
GVF •1024 •⏐VSENSE  
⏐
where V  
is the smallest sense voltage magnitude  
SENSE  
CHARGE  
INT  
before and after the polarity change.  
CLR  
Open-drain outputs POL and INT can sink I = 1.6mA  
OL  
LTC4150  
at V = 0.5V. The minimum pull-up resistance for these  
OL  
DISCHARGE  
pins should be:  
POL  
R > (V – 0.5)/1.6mA  
(11)  
L
CC  
4150 F04  
where V is the logic supply voltage. Because speed isn’t  
Figure 4. Unravelling Polarity—  
Separate Charge and Discharge Outputs  
CC  
an issue, pull-up resistors of 10k or higher are adequate.  
4150fc  
9
1...6789101112...14

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