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LTC2953IDD-2-TRPBF PDF预览

LTC2953IDD-2-TRPBF

更新时间: 2024-01-25 16:27:27
品牌 Logo 应用领域
凌特 - Linear 监控控制器
页数 文件大小 规格书
20页 199K
描述
Push Button On/Off Controller with Voltage Monitoring

LTC2953IDD-2-TRPBF 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:DFN包装说明:HVSON, SOLCC12,.12,20
针数:12Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.5可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUITJESD-30 代码:S-PDSO-N12
JESD-609代码:e3长度:3 mm
湿度敏感等级:1信道数量:1
功能数量:1端子数量:12
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVSON
封装等效代码:SOLCC12,.12,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.7/28 V认证状态:Not Qualified
座面最大高度:0.8 mm子类别:Power Management Circuits
最大供电电流 (Isup):0.026 mA最大供电电压 (Vsup):27 V
最小供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.45 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

LTC2953IDD-2-TRPBF 数据手册

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LTC2953  
APPLICATIONS INFORMATION  
to the low offset architecture of the comparators, the  
+
UVLO and PFI thresholds can be set to as close as 5mV  
apart. The trip thresholds of the circuit of Figure 14 are  
6.04V and 5.40V for the power fail and low battery (UVLO)  
comparators, respectively.  
8.4V  
V
INT  
EN  
LTC2953-1  
IN  
DEBOUNCE  
UVLO  
COMPARATOR  
R14  
2150k  
Push Button Lockout  
UVLO  
V
= 5.4V  
TH  
The LTC2953 provides a push button lock out feature that  
prevents a user from turning on a system with a dead  
battery. The push button input is ignored when the UVLO  
input voltage is less than the falling threshold (0.5V). See  
Figure 15B.  
DEBOUNCE  
AND DELAY  
50mV  
0.5V  
PFI  
+
R13  
23.2k  
PFO  
V
= 6.04V  
TH  
4mV  
R12  
196k  
SUPPLY  
GLITCH  
0.55V  
+
0.5V  
UVLO  
0.5V  
t
POWER FAIL  
COMPARATOR  
DB, OFF  
2953 F15a  
2953 F14  
INT  
t
INT, Min  
Figure 14. Dual Function Battery Comparators  
Figure 15A. Supply Glitch Generates μP Interrupt  
Which Input Initiated Power Down: PB or UVLO?  
The circuit in Figure 14 determines whether a power  
down was initiated by a user pressing the push button  
or by a battery drooping too low. If both INT and PFO  
outputs are low, then a low battery condition initiated a  
power down.  
UVLO  
INT  
0.5V  
LOW SUPPLY CONDITION  
t
DB, OFF  
PFI and UVLO Thresholds  
t
+ t  
PD, Min PDT  
The circuit depicted in Figure 14 uses one resistive divider  
network for both power fail and low battery comparators.  
The power fail comparator trips at a higher battery voltage  
than the low battery comparator, thus providing a battery  
warning before a power down sequence is initiated. Due  
LOW SUPPLY  
LOCKS OUT  
ENABLE  
EN  
2953 F15b  
Figure 15B. Low Supply Initiates System  
Power Down and Locks Out Enable  
2953f  
15  

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