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LTC2301

更新时间： 2023-12-20 18:44:04
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
26页 885K
描述
具有I2C兼容型接口的单通道、12位ADC

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中文翻译

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LTC2301 数据手册

 浏览型号LTC2301的Datasheet PDF文件第1页浏览型号LTC2301的Datasheet PDF文件第2页浏览型号LTC2301的Datasheet PDF文件第3页浏览型号LTC2301的Datasheet PDF文件第5页浏览型号LTC2301的Datasheet PDF文件第6页浏览型号LTC2301的Datasheet PDF文件第7页 
LTC2301/LTC2305  
DYNAMIC ACCURACY  
The l denotes the specifications which apply over the full operating temperature range,  
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4,9)  
SYMBOL  
SINAD  
SNR  
PARAMETER  
CONDITIONS  
MIN  
71  
TYP  
73.4  
73.5  
–91  
92  
MAX  
UNITS  
dB  
l
l
l
l
Signal-to-(Noise + Distortion) Ratio  
Signal-to-Noise Ratio  
f
IN  
f
IN  
f
IN  
f
IN  
f
IN  
f
IN  
= 1kHz  
= 1kHz  
71  
dB  
THD  
Total Harmonic Distortion  
Spurious Free Dynamic Range  
Channel-to-Channel Isolation  
Full Linear Bandwidth  
= 1kHz  
–77  
dB  
SFDR  
= 1kHz, First 5 Harmonics  
79  
dB  
= 1kHz  
= 1kHz  
–109  
700  
25  
dB  
kHz  
MHz  
ns  
–3dB Input Linear Bandwidth  
Aperture Delay  
(Note 10)  
13  
Transient Response  
Full-Scale Step  
240  
ns  
INTERNAL REFERENCE CHARACTERISTICS  
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
2.50  
25  
MAX  
UNITS  
V
l
V
V
V
V
V
Output Voltage  
Output Tempco  
Output Impedance  
I
I
= 0  
= 0  
2.46  
2.54  
REF  
OUT  
OUT  
ppm/°C  
kΩ  
REF  
–0.1mA ≤ I  
≤ 0.1mA  
8
REF  
OUT  
Output Voltage  
I
= 0  
4.096  
0.8  
V
REFCOMP  
OUT  
Line Regulation  
V
DD  
= 4.75V to 5.25V  
mV/V  
REF  
I2C INPUTS AND DIGITAL OUTPUTS  
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4)  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
l
l
l
l
V
V
V
V
High Level Input Voltage  
2.85  
V
V
IH  
Low Level Input Voltage  
1.5  
IL  
High Level Input Voltage for Address Pins A1, A0  
Low Level Input Voltage for Address Pins A1, A0  
4.75  
V
IHA  
ILA  
0.25  
10  
V
R
R
R
Resistance from A1, A0 to V to Set Chip  
Address Bit to 1  
kꢁ  
INH  
INL  
INF  
DD  
l
l
Resistance from A1, A0 to GND to Set Chip  
Address Bit to 0  
10  
kꢁ  
Resistance from A1, A0 to GND or V to Set  
Chip Address Bit to Float  
2
Mꢁ  
DD  
l
l
l
l
l
l
I
Digital Input Current  
V
= V  
DD  
–10  
10  
ꢀA  
V
I
IN  
V
Hysteresis of Schmitt Trigger Inputs  
Low Level Output Voltage (SDA)  
(Note 8)  
I = 3mA  
0.25  
HYS  
OL  
V
0.4  
250  
50  
V
t
OF  
t
SP  
Output Fall Time V  
to V  
Bus Load C 10pF to 400pF (Note 11)  
20 + 0.1C  
B
ns  
ns  
pF  
IN(MIN)  
IL(MAX)  
B
Input Spike Suppression  
C
External Capacitance Load on Chip Address Pins  
(A1, A0) for Valid Float  
10  
CAX  
23015fb  
4
1234567...26

中文翻译

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