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LTC1748

更新时间: 2023-12-20 18:44:16
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 528K
描述
14 位、80Msps 低噪声 ADC

LTC1748 数据手册

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LTC1748  
14-Bit, 80Msps Low Noise ADC  
U
FEATURES  
DESCRIPTIO  
The LTC®1748 is an 80Msps, sampling 14-bit A/D con-  
verter designed for digitizing high frequency, wide dy-  
namic range signals. Pin selectable input ranges of ±1V  
and ±1.6V along with a resistor programmable mode  
allowtheLTC1748’sinputrangetobeoptimizedforawide  
variety of applications.  
Sample Rate: 80Msps  
76.3dB SNR and 90dB SFDR (3.2V Range)  
72.6dB SNR and 90dB SFDR (2V Range)  
No Missing Codes  
Single 5V Supply  
Power Dissipation: 1.4W  
Selectable Input Ranges: ±1V or ±1.6V  
The LTC1748 is perfect for demanding communications  
applications with AC performance that includes 76.3dB  
SNRand90dBspuriousfreedynamicrange.Ultralowjitter  
of0.15psRMS allowsundersamplingofIFfrequencieswith  
excellentnoiseperformance.DCspecsinclude±3LSBINL  
and no missing codes.  
240MHz Full Power Bandwidth S/H  
Pin Compatible Family  
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)  
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)  
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)  
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)  
The digital interface is compatible with 5V, 3V, 2V and  
LVDS logic systems. The ENC and ENC inputs may be  
driven differentially from PECL, GTL and other low swing  
logic families or from single-ended TTL or CMOS. The low  
noise, high gain ENC and ENC inputs may also be driven  
by a sinusoidal signal without degrading performance. A  
separate output power supply can be operated from 0.5V  
to 5V, making it easy to connect directly to any low voltage  
DSPs or FIFOs.  
48-Pin TSSOP Package  
U
APPLICATIO S  
Telecommunications  
Receivers  
Cellular Base Stations  
Spectrum Analysis  
Imaging Systems  
The TSSOP package with a flow-through pinout simplifies  
the board layout.  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
W
BLOCK DIAGRA  
80Msps, 14-Bit ADC with a 2V Differential Input Range  
OV  
DD  
0.5V  
TO 5V  
0.1µF  
0.1µF  
+
A
IN  
OF  
D13  
CORRECTION  
LOGIC AND  
SHIFT  
±1V  
DIFFERENTIAL  
ANALOG INPUT  
14  
S/H  
AMP  
14-BIT  
PIPELINED ADC  
OUTPUT  
LATCHES  
D0  
CLKOUT  
A
REGISTER  
IN  
OGND  
SENSE  
BUFFER  
V
DD  
5V  
1µF  
1µF  
RANGE  
SELECT  
DIFF AMP  
1µF  
V
CM  
GND  
2.35V  
REF  
CONTROL LOGIC  
4.7µF  
1748 BD  
REFLB REFHA  
4.7µF  
REFLA REFHB ENC ENC MSBINV  
OE  
0.1µF  
0.1µF  
DIFFERENTIAL  
ENCODE INPUT  
1µF  
1µF  
1748fa  
1

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