Datasheet > LTC1661

LTC1661

更新时间： 2023-12-20 18:44:03

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
14页	239K
描述
MSOP 封装的微功率、双通道 10 位 DAC

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中文翻译

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LTC1661 数据手册

LTC1661

timing characteristics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

= 2.7V to 5.5V

Valid to SCK Setup

Valid to SCK Hold

(Note 6)

SCK High Time

(Note 6)

100

SCK Low Time

(Note 6)

CS/LD Pulse Width

(Note 6)

LSB SCK High to CS/LD High

CS/LD Low to SCK High

SCK Low to CS/LD Low

CS/LD High to SCK Positive Edge

SCK Frequency

(Note 6)

Square Wave (Note 6)

MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Nonlinearity and monotonicity are deﬁned from code 20 to code

1023 (full scale). See Applications Information.

Note 3: Digital inputs at 0V or V

Note 4: Load is 10kΩ in parallel with 100pF.

Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V ,

REF

i.e., codes k = 102 and k = 922.

Note 6: Guaranteed by design and not subject to test.

timing Diagram

SCK

CS/LD

1661 TD

1661fb

For more information www.linear.com/LTC1661

1 2 345 6 7...14

中文翻译

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