Datasheet > LTC1589

LTC1589

更新时间： 2023-12-20 18:44:06

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	276K
描述
具可编程输出范围的14位SoftSpan DAC

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数据手册

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LTC1589 数据手册

LTC1588/LTC1589/LTC1592

PI FU CTIO S

I_OUT1(Pin 5): True DAC Current Output. Tied to the

inverting input of the current-to-voltage op amp.

SCK (Pin 12): Serial Interface Clock. Data on the SDI pin

isshiftedintotheinputshiftregisteronrisingedgeofSCK.

I_OUT2(Pin 6): Complement of DAC Current Output. Nor-

CS/LD (Pin 13): Chip Select Input. When CS/LD is low,

SCKisenabledforshiftingdataintotheinputshiftregister.

WhenCS/LDispulledhigh,SCKisdisabledandthecontrol

logic executes the control word (the first 4 bits of the input

data stream as shown in Table 1).

mally tied to AGND pin.

AGND (Pin 7): Analog Ground. Tie to the system’s analog

ground plane.

GND (Pin 8): Ground. Tie to the system’s analog ground

plane.

CLR (Pin 14): When CLR is taken to a logic low, it sets the

DAC output to 0V and all internal registers to zero code.

V_CC(Pin 9): Positive Supply Input. 4.5V ≤ V_CC≥ 5.5V.

Requires a 0.1µF bypass capacitor to ground.

REF (Pin 15): DAC Reference Input. Typically 5V, accepts

up to ±15V.

SDO(Pin10): SerialDataOutput. Dataatthispinisshifted

out on the rising edge of SCK.

R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC

referenceinputREF(Pin15)andtheoutputoftheinverting

amplifier tied to R_COM(Pin 1).

SDI (Pin 11): Serial Data Input.

FU CTIO TABLE

Table 1

Internal Register Status

SREG

DATA WORD

Dn IN INPUT

BUF1

BUF2

DAC

BUFFER

(DAC OUTPUT)

No Change

COMMAND

OPERATION

EACH COMMAND IS EXECUTED

ON THE RISING EDGE OF CS/LD

DAC

OUTPUT

RANGE

No Change

INPUT

C3 C2 C1 C0

SHIFT REGISTER BUFFER

Copy Data Word Dn in SReg to Buf1

Copy the Data in Buf1 to Buf2

Copy Data Word Dn in SReg to Buf1 and Buf2

Reserved (Do Not Use)

Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2

Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2

Set Range to ±5V. Copy Dn in SReg to Buf1 and Buf2

Set Range to ±10V. Copy Dn in SReg to Buf1 and Buf2

Set Range to ±2.5V. Copy Dn in SReg to Buf1 and Buf2

Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2

Reserved (Do Not Use)

10V

±5V

±10V

±2.5V

–2.5V to 7.5V

No Change No Change

No Change

No Operation

Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.

1588992fa

1...4 5 678 9 10...16

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