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LTC1326CS8-2.5#TR PDF预览

LTC1326CS8-2.5#TR

更新时间： 2024-02-24 04:07:35
品牌 Logo 应用领域
亚德诺 - ADI 输入元件光电二极管
页数 文件大小 规格书
16页 207K
描述
LTC1326 - Micropower Precision Triple Supply Monitor; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C

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LTC1326CS8-2.5#TR 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：SOIC包装说明：0.150 INCH, PLASTIC, SOP-8
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.24其他特性：RESET THRESHOLD VOLTAGE IS 2.363; MANUAL PUSH-BUTTON RESET INPUT
可调阈值：NO模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9025 mm湿度敏感等级：1
信道数量：3功能数量：3
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：235电源：3.3,5 V
认证状态：Not Qualified座面最大高度：1.752 mm
子类别：Power Management Circuits最大供电电流 (Isup)：0.04 mA
最大供电电压 (Vsup)：7 V最小供电电压 (Vsup)：1 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
阈值电压标称：1.0,2.363,3.118V处于峰值回流温度下的最长时间：20
宽度：3.899 mm

LTC1326CS8-2.5#TR 数据手册

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LTC1326/LTC1326-2.5  
U W  
TYPICAL PERFOR A CE CHARACTERISTICS  
Reset Pulse Width  
vs Temperature  
PBR Assertion Time to Reset  
vs Temperature  
“Soft” Reset Pulse Width  
vs Temperature  
112.5  
110.0  
107.5  
105.0  
102.5  
100.0  
97.5  
2.25  
2.20  
2.15  
2.10  
2.05  
2.00  
1.95  
1.90  
225  
220  
215  
210  
205  
200  
195  
190  
95.0  
–60  
20  
TEMPERATURE (°C)  
60 80  
–60  
80  
–60  
20  
60 80  
–40 –20  
0
40  
100  
–40 –20  
0
20 40 60  
100  
–40 –20  
0
40  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
1326/2.5 G14  
1326/2.5 G15  
1326/2.5 G13  
U
U
U
PIN FUNCTIONS  
VCC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for RST (Pin 6): Reset Logic Output. Active low, open-drain  
the IC. Bypass to ground with ≥ 0.1µF ceramic capacitor. logic output with weak pull-up to VCC3. Can be pulled up  
greater than VCC3 when interfacing to 5V logic. Asserted  
VCC5 (Pin 2) (LTC1326): 5V Sense Input. Used as gate  
when one or more of the supplies are below trip  
drive for the RST output FET when the voltage on VCC3 is  
thresholds and held for 200ms after all supplies become  
less than the voltage on VCC5. If unused, it can be tied to  
valid. Also asserted after PBR is held low for more than  
VCC3 (see Dual and Single Supply Monitor Operation in  
2 seconds and for an additional 200ms after PBR is  
the Applications Information section).  
released.  
VCC25 (Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as  
SRST (Pin 7): Soft Reset. Active low, open-drain logic  
gate drive for RST output FET when the voltage on VCC3  
output with weak pull-up to VCC3. Can be pulled up  
is less than the voltage on VCC25. If unused, it can be tied  
greater than VCC3 when interfacing to 5V logic. Asserted  
to VCC3  
.
for 100µs after PBR is held low for less than 2 seconds  
VCCA (Pin 3): 1V Sense, High Impedance Input. Can be  
and released.  
used as a logic input with a 1V threshold. If unused, it can  
PBR (Pin 8): Push-Button Reset. Active low logic input  
with weak pull-up to VCC3. Can be pulled up greater than  
VCC3 wheninterfacingto5Vlogic. Whenassertedforless  
than 2 seconds, outputs a soft reset 100µs pulse on the  
SRST pin. When PBR is asserted for greater than 2  
seconds, the RST output is forced low and remains low  
until 200ms after PBR is released.  
be tied to either VCC3 or VCC25  
.
GND (Pin 4): Ground.  
RST (Pin 5):Reset Logic Output. Active high CMOS logic  
output,driveshightoVCC3,bufferedcomplementofRST.  
An external pull-down on the RST pin will drive this pin  
high.  
132625fc  
6
1...3456789...16

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