LT3959
pin FuncTions
DRIVE: DRIVE LDO Supply Pin. This pin can be connected
NC: No Internal Connection. Leave these pins open or
to either V or a quasi-regulated voltage supply such as a
connect them to the adjacent pins.
IN
DC converter output. This pin must be bypassed to GND
PGOOD: Output Ready Status Pin. An open-collector pull
with a minimum of 1µF capacitor placed close to the pin.
down on PGOOD asserts when INTV is greater than
CC
Tie this pin to V if not used.
IN
2.7V and the FBX voltage is within 5% (80mV if V
1.6V or 40mV if V = –0.8V) of the regulation voltage.
=
FBX
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.22V (nominal) falling threshold with externally
programmable hysteresis detects when power is okay to
enable switching. Rising hysteresis is generated by the
external resistor divider and an accurate internal 2.2μA
pull-down current. An undervoltage condition resets soft-
start. Tie to 0.4V, or less, to disable the device and reduce
FBX
RT: SwitchingFrequencyAdjustmentPin.Setthefrequency
using a resistor to SGND. Do not leave the RT pin open.
SGND: Signal Ground. Must be soldered directly to the
signal ground plane. Connect to ground terminal of: ex-
ternal resistor dividers for FBX and EN/UVLO; capacitors
for INTV , SS, and V ; and resistor R .
V quiescent current below 1μA.
IN
CC
C
T
SS: Soft-Start Pin. This pin modulates compensation pin
FBX: Voltage Regulation Feedback Pin for Positive or
Negative Outputs. Connect this pin to a resistor divider
betweentheoutputandSGND.FBXistheinputoftwoerror
amplifiers—one configured to regulate a positive output;
the other, a negative output. Depending upon topology
selected, switching causes the output to ramp positive or
negative. The appropriate amplifier takes control while the
other becomes inactive. Additionally FBX is input for two
window comparators that indicate through the PGOOD
pin when the output is within 5% of the regulation volt-
ages. FBX also modulates the switching frequency during
start-up and fault conditions when FBX is close to SGND.
voltage (V ) clamp. The soft-start interval is set with an
C
external capacitor. The pin has a 10µA (typical) pull-up
current source to an internal 2.5V rail. The soft-start pin
is reset to SGND by an EN/UVLO undervoltage condition,
an INTV undervoltage condition or an internal thermal
CC
lockout.
SW: Drain of Internal Power N-Channel MOSFET.
SYNC:FrequencySynchronizationPin.Usedtosynchronize
the internal oscillator to an outside clock. If this feature is
used,anR resistorshouldbechosentoprogramaswitch-
T
ing frequency 20% slower than SYNC pulse frequency.
Tie the SYNC pin to SGND if this feature is not used. This
signal is ignored during FB frequency foldback or when
GND: Source Terminal of Switch and the GND Input to the
Switch Current Comparator.
INTV is less than 2.7V.
GNDK: Kelvin Connection Pin between GND and SGND.
Kelvin connect this pin to the SGND plane close to the IC.
See the Board Layout section.
CC
V : Supply Pin for Internal Leads and the V LDO Regu-
IN
IN
lator of INTV . Must be locally bypassed to GND with a
CC
minimum of 1µF capacitor placed close to this pin.
INTV : Regulated Supply for Internal Loads and Gate
CC
Driver. Regulated to 4.75V if powered from DRIVE or
V : Error Amplifier Compensation Pin. Used to stabilize
C
regulated to 3.75V if powered from V . The INTV pin
IN
CC
the voltage loop with an external RC network. Place com-
must be bypassed to SGND with a minimum of 4.7µF
pensation components between the V pin and SGND.
C
capacitor placed close to the pin.
3959fa
7
For more information www.linear.com/LT3959
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