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LT1016

更新时间： 2023-12-20 18:44:06
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 浏览型号LT1016的Datasheet PDF文件第1页浏览型号LT1016的Datasheet PDF文件第2页浏览型号LT1016的Datasheet PDF文件第4页浏览型号LT1016的Datasheet PDF文件第5页浏览型号LT1016的Datasheet PDF文件第6页浏览型号LT1016的Datasheet PDF文件第7页 
LT1016  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.  
LT1016C/I  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
Input Offset Voltage  
R ≤ 100Ω (Note 2)  
1.0  
3
mV  
mV  
OS  
S
●
●
3.5  
∆V /∆T  
Input Offset Voltage Drift  
Input Offset Current  
4
µV/°C  
OS  
I
OS  
(Note 2)  
(Note 3)  
0.3  
0.3  
1.0  
1.3  
µA  
µA  
●
●
I
B
Input Bias Current  
5
10  
13  
µA  
µA  
Input Voltage Range  
(Note 6)  
Single 5V Supply  
●
●
–3.75  
1.25  
3.5  
3.5  
V
V
CMRR  
PSRR  
Common Mode Rejection  
Supply Voltage Rejection  
–3.75V ≤ V ≤ 3.5V  
●
●
80  
60  
96  
75  
dB  
dB  
CM  
+
Positive Supply 4.6V ≤ V ≤ 5.4V  
LT1016C  
+
Positive Supply 4.6V ≤ V ≤ 5.4V  
●
●
54  
75  
dB  
LT1016I  
–
Negative Supply 2V ≤ V ≤ 7V  
80  
100  
dB  
A
V
Small-Signal Voltage Gain  
Output High Voltage  
1V ≤ V  
≤ 2V  
1400  
3000  
V/V  
V
OUT  
+
V ≥ 4.6V  
I
I
=1mA  
= 10mA  
●
●
2.7  
2.4  
3.4  
3.0  
V
V
OH  
OUT  
OUT  
V
Output Low Voltage  
I
I
= 4mA  
= 10mA  
●
0.3  
0.4  
0.5  
V
V
OL  
SINK  
SINK  
+
I
I
Positive Supply Current  
Negative Supply Current  
LATCH Pin Hi Input Voltage  
LATCH Pin Lo Input Voltage  
LATCH Pin Current  
●
●
●
●
●
25  
3
35  
5
mA  
mA  
V
–
V
V
2.0  
IH  
0.8  
V
IL  
I
t
V
= 0V  
500  
µA  
IL  
PD  
LATCH  
Propagation Delay (Note 4)  
∆V = 100mV, OD = 5mV  
10  
9
14  
16  
ns  
ns  
IN  
●
●
∆V = 100mV, OD = 20mV  
12  
15  
ns  
ns  
IN  
∆t  
Differential Propagation Delay  
Latch Setup Time  
(Note 4) ∆V = 100mV,  
3
ns  
PD  
IN  
OD = 5mV  
2
ns  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
limits shown can be guaranteed with this test if additional DC tests are  
performed to guarantee that all internal bias conditions are correct. For low  
overdrive conditions V is added to overdrive. Differential propogation  
OS  
delay is defined as: ∆t = t  
– t  
PD  
PDLH  
PDHL  
Note 2: Input offset voltage is defined as the average of the two voltages  
measured by forcing first one output, then the other to 1.4V. Input offset  
current is defined in the same way.  
Note 5: Electrical specifications apply only up to 5.4V.  
Note 6: Input voltage range is guaranteed in part by CMRR testing and  
in part by design and characterization. See text for discussion of input  
voltage range for supplies other than 5V or 5V.  
Note 3: Input bias current (I ) is defined as the average of the two input  
B
currents.  
Note 7: This parameter is guaranteed to meet specified performance  
Note 4: t and ∆t cannot be measured in automatic handling equipment  
through design and characterization. It has not been tested.  
PD  
PD  
with low values of overdrive. The LT1016 is sample tested with a 1V step  
and 500mV overdrive. Correlation tests have shown that t and ∆t  
PD  
PD  
Rev D  
3
For more information www.analog.com  
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