LR38575

更新时间： 2024-02-26 16:34:37

品牌	Logo	应用领域
夏普 - SHARP		模拟IC 信号电路 ISM频段
页数	文件大小	规格书
9页	93K
描述
Timing Generator IC for 1 310 k-pixel CCD

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技术参数
数据手册

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LR38575 技术参数

生命周期：	Obsolete	包装说明：	7 X 7 MM, 0.50 MM PITCH, PLASTIC, QFP-48
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	其他特性：	ALSO REQUIRES 4.5V SUPPLY
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e6	长度：	7 mm
功能数量：	1	端子数量：	48
最高工作温度：	70 °C	最低工作温度：	-20 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.85 mm	最大供电电压 (Vsup)：	4.5 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	TIN BISMUTH
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	Base Number Matches：	1

LR38575 数据手册

LR38575

PIN NO. SYMBOL IO SYMBOL POLARITY

PIN NAME

DESCRIPTION

A pulse to clamp the optical black signal.

This pulse is controlled by serial data BCPCNT;

BCPCNT = H; This pulse stays high during the

absence of effective pixels within the

vertical blanking or during the

Optical black clamp

pulse output

14 BCPX

sweepout signal.

BCPCNT = L; This pulse stays high during the

sweepout signal.

A pulse to clamp the dummy outputs of the CCD signal.

This pulse stays high during the sweepout period.

An output pin for AD converter. The output phase of

ADCK is selected by serial data in 90˚ steps.

A grounding pin.

15 CLPX

Clamp pulse output

O6MA3

–

16 ADCK

17 GND

AD clock output

Ground

–

A pulse to clamp the feed-through level for the CCD.

18 FCDS

O6MA3

CDS pulse output 1 The output phase and output polarity of FCDS are

selected by serial data.

A pulse to sample-hold the signal for the CCD.

CDS pulse output 2 The output phase and output polarity of FS are selected

by serial data.

19 FS

O6MA3

–

20 VDD3

21 ACLX

–

Power supply

Supply of +3.3 V power.

An input pin for resetting all internal circuits at power-on.

Connect to VDD through the diode and GND through the

capacitor.

ICU3

All clear input

A pulse to sample-hold the signal for the CDS circuit.

The output polarity of RS is selected by serial data.

A grounding pin.

22 RS

O6MA3

–

S/H pulse output

Ground

23 GND

–

An input pin to control internal vertical clock for long

shutter speed.

H level or open

L level

: VD

24 VCON

ICU3

VD control input

: VD is masked by the pulse which

is latched at the rising edge of VD.

It's necessary to be set SMD = high and number of the

fields data n ≥ 2 in serial data control at VCON operation.

An input pin for reference clock oscillation.

The frequency is 24.54545 MHz.

25 CKI

26 CKO

27 CLK

OSCI3

OSCO3

O6MA3

–

Clock input

Clock output

An output pin for reference clock oscillation.

The output is the inverse of CKI (pin 25).

An output pin to generate HD and VD pulses.

The frequency is 12.272725 MHz.

1 2 345 6 7...9

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