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LPC18S30FET256E PDF预览

LPC18S30FET256E

更新时间: 2023-12-18 00:00:00
品牌 Logo 应用领域
恩智浦 - NXP PC静态存储器外围集成电路
页数 文件大小 规格书
151页 2921K
描述
LPC18S30FET256 - 32-bit ARM Cortex-M3 flashless MCU with security features; 200 kB SRAM; Ethernet, two HS USB, EMC BGA 256-Pin

LPC18S30FET256E 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:BGA包装说明:,
针数:256Reach Compliance Code:compliant
风险等级:2.35湿度敏感等级:3
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

LPC18S30FET256E 数据手册

 浏览型号LPC18S30FET256E的Datasheet PDF文件第1页浏览型号LPC18S30FET256E的Datasheet PDF文件第3页浏览型号LPC18S30FET256E的Datasheet PDF文件第4页浏览型号LPC18S30FET256E的Datasheet PDF文件第5页浏览型号LPC18S30FET256E的Datasheet PDF文件第6页浏览型号LPC18S30FET256E的Datasheet PDF文件第7页 
LPC18S50/S30/S10  
NXP Semiconductors  
32-bit ARM Cortex-M3 microcontroller  
Crystal oscillator with an operating range of 1 MHz to 25 MHz.  
12 MHz internal RC oscillator trimmed to 1.5 % accuracy over temperature and  
voltage.  
Ultra-low power RTC crystal oscillator.  
Three PLLs allow CPU operation up to the maximum CPU rate without the need for  
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the  
third PLL can be used as audio PLL.  
Clock output.  
Configurable digital peripherals:  
State Configurable Timer (SCTimer/PWM) subsystem on AHB.  
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and  
outputs to event driven peripherals like timers, SCTimer/PWM, and ADC0/1.  
Serial interfaces:  
Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to  
52 MB per second.  
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high  
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time  
stamping (IEEE 1588-2008 v2).  
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and  
on-chip high-speed PHY (USB0).  
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip  
full-speed PHY and ULPI interface to an external high-speed PHY (USB1).  
USB interface electrical test software included in ROM USB stack.  
Four 550 UARTs with DMA support: one UART with full modem interface; one  
UART with IrDA interface; three USARTs support UART synchronous mode and a  
smart card interface conforming to ISO7816 specification.  
Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller  
excludes operation of all other peripherals connected to the same bus bridge See  
Figure 1 and Ref. 2.  
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA  
support.  
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O  
pins conforming to the full I2C-bus specification. Supports data rates of up to  
1 Mbit/s.  
One standard I2C-bus interface with monitor mode and standard I/O pins.  
Two I2S interfaces with DMA support, each with one input and one output.  
Digital peripherals:  
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,  
and SDRAM devices.  
LCD controller with DMA support and a programmable display resolution of up to  
1024 H 768 V. Supports monochrome and color STN panels and TFT color  
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel  
mapping.  
Secure Digital Input Output (SD/MMC) card interface.  
Eight-channel General-Purpose DMA controller can access all memories on the  
AHB and all DMA-capable AHB slaves.  
LPC18S50_S30_S10  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2016. All rights reserved.  
Product data sheet  
Rev. 1.2 — 8 March 2016  
2 of 151  

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