Datasheet > LP62S2048V-10LLT

LP62S2048V-10LLT

更新时间： 2022-11-25 21:52:21

品牌	Logo	应用领域
联笙电子 - AMICC		静态存储器
页数	文件大小	规格书
17页	192K
描述
256K X 8 BIT LOW VOLTAGE CMOS SRAM

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LP62S2048V-10LLT 数据手册

LP62S2048-T Series

256K X 8 BIT LOW VOLTAGE CMOS SRAM

Features

nPower supply range: 2.7V to 3.3V

nAccess times: 70/100 ns (max.)

nCurrent:

nAll inputs and outputs are directly TTL-compatible

nCommon I/O using three-state output

nOutput enable and two chip enable inputs for easy

application

Low power version:

Operating: 30mA (max.)

nData retention voltage: 2V (min.)

Standby: 50mA (max.)

nAvailable in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)

and 36-pin CSP packages

Very low power version: Operating: 30mA (max.)

Standby: 10mA (max.)

nFull static operation, no clock or refreshing required

General Description

The LP62S2048-T is a low operating current 2,097,152-

bit static random access memory organized as 262,144

words by 8 bits and operates on a low power supply

range: 2.7V to 3.3V. It is built using AMIC's high

performance CMOS process.

Two chip enable inputs are provided for POWER-DOWN

and device enable and an output enable input is included

for easy interfacing.

Data retention is guaranteed at a power supply voltage

as low as 2V.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Pin Configurations

n SOP

n TSOP/(TSSOP)

n CSP (Chip Size Package)

36-pin Top View

VCC

A15

CE2

A13

A17

A16

A14

A12

CE2

I/O

I/O1

A11

I/O2

GND

VCC

GND

A10

CE1

I/O⁸

I/O

CE1

A11

A17

A16

A12

I/O

I/O1

I/O²

I/O7

I/O6

I/O5

I/O4

I/O

A15

A13

A10

A14

I/O3

GND

Pin No.

CE2 A15 VCC A17 A16

22 23 24 25 26

I/O

A14

A12

Name

A11

A13 WE

Pin No.

I/O

Name

I/O8

I/O GND I/O I/O

I/O6

I/O7

CE1 A10

(August, 2001, Version 1.0)

AMIC Technology, Inc.

12 3 4 5 6 7...17

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