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LNK3204P PDF预览

LNK3204P

更新时间: 2024-01-22 12:21:08
品牌 Logo 应用领域
帕沃英蒂格盛 - POWERINT /
页数 文件大小 规格书
22页 1875K
描述
IC OFFLN CONV MULT TOP 8DIP

LNK3204P 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:14 weeks
风险等级:1.74峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

LNK3204P 数据手册

 浏览型号LNK3204P的Datasheet PDF文件第5页浏览型号LNK3204P的Datasheet PDF文件第6页浏览型号LNK3204P的Datasheet PDF文件第7页浏览型号LNK3204P的Datasheet PDF文件第9页浏览型号LNK3204P的Datasheet PDF文件第10页浏览型号LNK3204P的Datasheet PDF文件第11页 
LNK3202/3204-6  
Topology  
Basic Circuit Schematic  
Key Features  
1. Output referenced to input  
+
2. Positive output (VO) with respect to +VIN  
3. Step up/down – VO > VIN or VO < VIN  
4. Optocoupler feedback  
Low-Side  
LinkSwitch-TN2  
VIN  
VO  
Buck-Boost –  
Optocoupler  
Feedback  
- Accuracy only limited by reference choice  
- Low cost non-safety rated optocoupler  
- No pre-load required  
BP/M  
FB  
+
5. Fail-safe – output is not subjected to input  
voltage if the internal power MOSFET fails  
6. Minimum no-load consumption  
S
D
PI-7848-031616  
Table 3 (cont). Common Circuit Configurations using LinkSwitch-TN2.  
Figures 9a, 9b and 9c are printed circuit board layout design  
examples for the circuit schematic shown in Figure 8. The loop  
formed between the LinkSwitch-TN2, inductor (L1), freewheeling  
diode (D1), and output capacitor (C2) should be kept as small as  
possible. The BYPASS pin capacitor C1 should be located physically  
close to the SOURCE (S) and BYPASS (BP) pins. To minimize direct  
coupling from switching nodes, the LinkSwitch-TN2 should be placed  
away from AC input lines. It may be advantageous to place capacitors  
C4 and C5 in-between LinkSwitch-TN2 and the AC input. The second  
rectifier diode D4 is optional, but may be included for better EMI  
performance and higher line surge withstand capability.  
LinkSwitch-TN2 Layout Considerations  
In the buck or buck-boost converter configuration, since the SOURCE  
pins in LinkSwitch-TN2 are switching nodes, the copper area  
connected to SOURCE should be minimized to minimize EMI within  
the thermal constraints of the design.  
In the boost configuration, since the SOURCE pins are tied to DC  
return, the copper area connected to SOURCE can be maximized to  
improve heat sinking.  
Figure 9a. Recommended Printed Circuit Layout for LinkSwitch-TN2 using P Package.  
8
Rev. F 01/17  
www.power.com  

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