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LMX2370SLDX

更新时间： 2024-01-01 06:16:18

品牌	Logo	应用领域
美国国家半导体 - NSC		射频个人通信
页数	文件大小	规格书
16页	220K
描述
IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, QCC24, 3.50 X 4.50 MM, 0.8 MM HEIGHT, TCSP-24, PLL or Frequency Synthesis Circuit

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LMX2370SLDX 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSSOP,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.7
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3	长度：	6.5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4.4 mm
Base Number Matches：	1

LMX2370SLDX 数据手册

1.0 Functional Description (Continued)

The reference oscillator input block is powered down when both Main_PWDN and Aux_PWDN bits are asserted. The OSC_inpin

reverts to a high impedance state when this condition exists. Power down forces the respective charge pump and phase com-

parator logic to a TRI-STATE condition. During the power down condition, both N- and R-counters are held at reset. Upon pow-

ering up, the N-counter resumes counting in “close” alignment with the R-counter. The maximum error is at most one prescaler

cycle. The MICROWIRE interface remains active and it is capable of loading and latching in data during all of the power down

modes.

2.0 Programming Description

2.1 MICROWIRE INTERFACE

The LMX237X register set can be accessed through the MICROWIRE interface. A 22-bit shift register is used as a temporary reg-

ister to indirectly program the on-chip registers. The shift register consists of a 20-bit DATA[19:0] field and a 2-bit ADDRESS[1:0]

field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in

the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored

in the shift register is loaded into the addressed latch.

MSB

LSB

ADDRESS[1:0]

DATA[19:0]

2.1.1 Registers’ Address Map

When Load Enable (LE) is transitioned high, data is transferred from the 22-bit shift register into the appropriate latch depending

on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the corre-

sponding internal register.

ADDRESS[1:0]

FIELD

ADDRESSED

Aux_R Register

Aux_N Register

Main_R Register

Main_N Register

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与LMX2370SLDX相关器件

型号	品牌	描述	获取价格	数据表
LMX2370TM	NSC	PLLatinum⑩ Dual Frequency Synthesizer for RF	获取价格
LMX2370TM	TI	PLL FREQUENCY SYNTHESIZER, 2500MHz, PDSO20, PLASTIC, TSSOP-20	获取价格
LMX2370TM/NOPB	TI	PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20	获取价格
LMX2370TMX	NSC	PLLatinum⑩ Dual Frequency Synthesizer for RF	获取价格
LMX2370TMX	TI	PLL FREQUENCY SYNTHESIZER, 2500MHz, PDSO20, PLASTIC, TSSOP-20	获取价格
LMX2370TMX/NOPB	TI	PLL FREQUENCY SYNTHESIZER, 2500MHz, PDSO20, PLASTIC, TSSOP-20	获取价格

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