Logic Electrical Characteristics (Continued)
DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for V+ = 2.65V to 3.6V for the
LM74CIBP -3, LM74CITP-3, V+ = 3.0V to 3.6V for the LM74CIM -3 and V+ = 4.5V to 5.5V for the LM74 -5 (Note 6). Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ=+25˚C, unless otherwise noted.
Typical
(Note 7)
−0.005
20
Limits
(Note 8)
−3.0
Units
(Limit)
µA (min)
pF
Symbol
IIN(0)
Parameter
Conditions
VIN = 0V
Logical “0” Input Current
All Digital Inputs
CIN
VOH
High Level Output Voltage
Low Level Output Voltage
TRI-STATE Output Leakage
Current
IOH = −400 µA
IOL = +2 mA
VO = GND
VO = V+
2.4
0.4
−1
V (min)
V (max)
µA (min)
µA
VOL
IO_TRI-STATE
+1
(max)
SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for V+ = 2.65V
to 3.6V for the LM74CIBP -3, LM74CITP-3, V+ = 3.0V to 3.6V for the LM74CIM -3 and V+ = 4.5V to 5.5V for the LM74 -5
(Note 6); CL (load capacitance) on output lines = 100 pF unless otherwise specified. Boldface limits apply for TA = TJ
TMIN to TMAX; all other limits TA = TJ = +25˚C, unless otherwise noted.
=
Typical
(Note 7)
Limits
(Note 8)
0.16
DC
Units
(Limit)
Symbol
t1
Parameter
Conditions
SC (Clock) Period
µs (min)
(max)
t2
t3
t4
t5
t6
t7
CS Low to SC (Clock) High Set-Up Time
CS Low to Data Out (SO) Delay
100
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
70
SC (Clock) Low to Data Out (SO) Delay
CS High to Data Out (SO) TRI-STATE
SC (Clock) High to Data In (SI) Hold Time
Data In (SI) Set-Up Time to SC (Clock) High
100
200
50
30
10090904
FIGURE 2. Data Output Timing Diagram
5
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