Datasheet > LM49450_15

LM49450_15

更新时间： 2022-02-26 11:50:33

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
42页	1037K
描述
Boomer I2S Input, 2.5W/Channel, Low EMI, Stereo, Class D Audio Sub-System with Ground Referenced Headphone Amplifier, 3D Enhancement, and Headphone Sense

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LM49450_15 数据手册

LM49450

www.ti.com

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Timing Characteristics⁽¹⁾⁽²⁾(continued)

The following specifications apply for Headphone: A_V= 0dB, R_L(LS)= 8Ω, R_L(HP)= 32Ω, f = 1kHz, unless otherwise specified.

Limits apply for T_A= 25°C.

LM49450

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽³⁾

Limit⁽⁴⁾

DATA Hold Time from BCLK

Rising Edge

ns (min)

t_DHT

CONTROL INTERFACE TIMING

SCLK Frequency

400

0.6

kHz (max)

Hold Time (repeated START

μs (min)

Condition)

Clock Low Time

Clock High Time

1.3

600

μs (min)

ns (min)

Setup Time for a Repeated

START Condition

Data Hold Time

Output

Input

300

ns (min)

900

ns (min)

ns (max)

Data Setup Time

100

ns (min)

20+0.1C_B

300

ns (min)

ns (max)

Rise Time of SDA and SCL

Fall Time of SDA and SCL

15+0.1C_B

300

ns (min)

ns (max)

Setup Time for STOP Condition

600

1.3

ns (min)

Bus Free time Between a STOP

and START Condition

μs ( min)

Bus Capacitance

200

pF (min)

pF (max)

C_B

PIN DESCRIPTIONS

Name

C1P

Description

Charge Pump Flying Capacitor Positive Terminal

Charge Pump Ground

I²C Serial Data Input

CPGND

SDA

DGND

I²S_WS

I²S_SDI

I²S_CLK

MCLK

SCL

Digital Ground

I²S Word Select Input

I²S Serial Data Input

I²S Clock Input

Master Clock

I²C Clock Input

18, 24

DV_DD

IOV_DD

GND

Digital Core Power Supply

Digital Interface Power Supply

Analog Ground

REF

DAC Reference Bypass

Right Channel Analog Input

Left Channel Analog Input

Analog Power Supply

INR

INL

V_DD

BYPASS

LSV_DD

LLS+

Mid-Rail Bias Bypass

Speaker Power Supply

Left Channel Non-Inverting Speaker Output

Left Channel Inverting Speaker Output

Speaker Ground

LLS-

LSGND

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