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LM2524 PDF预览

LM2524

更新时间: 2024-01-28 13:35:26
品牌 Logo 应用领域
美国国家半导体 - NSC 脉冲
页数 文件大小 规格书
22页 1167K
描述
Regulating Pulse Width Modulator

LM2524 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:N控制模式:VOLTAGE-MODE
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出电流:0.05 A
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
子类别:Switching Regulator or Controllers表面贴装:NO
技术:BIPOLAR温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

LM2524 数据手册

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March 2005  
LM2524D/LM3524D  
Regulating Pulse Width Modulator  
one pulse per period even in noisy environments. The  
LM3524D includes double pulse suppression logic that in-  
sures when a shut-down condition is removed the state of  
the T-flip-flop will change only after the first clock pulse has  
arrived. This feature prevents the same output from being  
pulsed twice in a row, thus reducing the possibility of core  
saturation in push-pull designs.  
General Description  
The LM3524D family is an improved version of the industry  
standard LM3524. It has improved specifications and addi-  
tional features yet is pin for pin compatible with existing 3524  
families. New features reduce the need for additional exter-  
nal circuitry often required in the original version.  
The LM3524D has a 1% precision 5V reference. The cur-  
rent carrying capability of the output drive transistors has  
been raised to 200 mA while reducing VCEsat and increasing  
VCE breakdown to 60V. The common mode voltage range of  
the error-amp has been raised to 5.5V to eliminate the need  
for a resistive divider from the 5V reference.  
Features  
n Fully interchangeable with standard LM3524 family  
n
1% precision 5V reference with thermal shut-down  
n Output current to 200 mA DC  
n 60V output capability  
In the LM3524D the circuit bias line has been isolated from  
the shut-down pin. This prevents the oscillator pulse ampli-  
tude and frequency from being disturbed by shut-down. Also  
at high frequencies (.300 kHz) the max. duty cycle per  
output has been improved to 44% compared to 35% max.  
duty cycle in other 3524s.  
n Wide common mode input range for error-amp  
n One pulse per period (noise suppression)  
n Improved max. duty cycle at high frequencies  
n Double pulse suppression  
n Synchronize through pin 3  
In addition, the LM3524D can now be synchronized exter-  
nally, through pin 3. Also a latch has been added to insure  
Connection Diagram  
00865002  
Top View  
Order Number LM2524DN or LM3524DN  
See NS Package Number N16E  
Order Number LM3524DM  
See NS Package Number M16A  
© 2005 National Semiconductor Corporation  
DS008650  
www.national.com  

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