CrossLink-NX Family
Preliminary Data Sheet
Contents
Acronyms in This Document.................................................................................................................................................9
1. General Description....................................................................................................................................................10
1.1.
Features ............................................................................................................................................................10
2. Architecture................................................................................................................................................................13
2.1.
2.2.
Overview ...........................................................................................................................................................13
PFU Blocks.........................................................................................................................................................15
2.2.1. Slice...............................................................................................................................................................15
2.2.2. Modes of Operation......................................................................................................................................18
2.2.2.1.
2.2.2.2.
2.2.2.3.
2.2.2.4.
Logic Mode...........................................................................................................................................18
Ripple Mode.........................................................................................................................................18
RAM Mode ...........................................................................................................................................18
ROM Mode...........................................................................................................................................18
2.3.
Routing..............................................................................................................................................................19
2.3.1. Clocking Structure.........................................................................................................................................19
2.3.2. Global PLL .....................................................................................................................................................19
2.3.3. Clock Distribution Network...........................................................................................................................20
2.3.4. Primary Clocks ..............................................................................................................................................21
2.3.5. Edge Clock.....................................................................................................................................................22
2.3.6. Clock Dividers................................................................................................................................................22
2.3.7. Clock Center Multiplexor Blocks...................................................................................................................23
2.3.8. Dynamic Clock Select....................................................................................................................................23
2.3.9. Dynamic Clock Control..................................................................................................................................24
2.3.10.
DDRDLL.....................................................................................................................................................24
2.4.
2.5.
SGMII Clock Data Recovery (CDR).....................................................................................................................25
sysMEM Memory ..............................................................................................................................................26
2.5.1. sysMEM Memory Block ................................................................................................................................26
2.5.2. Bus Size Matching.........................................................................................................................................27
2.5.3. RAM Initialization and ROM Operation ........................................................................................................27
2.5.4. Memory Cascading .......................................................................................................................................27
2.5.5. Single, Dual and Pseudo-Dual Port Modes ...................................................................................................27
2.5.6. Memory Output Reset..................................................................................................................................27
2.6.
2.7.
Large RAM.........................................................................................................................................................28
sysDSP ...............................................................................................................................................................28
2.7.1. sysDSP Approach Compared to General DSP................................................................................................28
2.7.2. sysDSP Architecture Features.......................................................................................................................29
2.8.
2.9.
ALUREG .............................................................................................................................................................31
Programmable I/O (PIO)....................................................................................................................................31
2.10. Programmable I/O Cell (PIC) .............................................................................................................................31
2.10.1. Input Register Block..................................................................................................................................33
2.10.2.1. Input FIFO.............................................................................................................................................33
2.10.2.
Output Register Block...............................................................................................................................34
2.11. Tristate Register Block.......................................................................................................................................35
2.12. DDR Memory Support.......................................................................................................................................36
2.12.1.
2.12.2.
DQS Grouping for DDR Memory...............................................................................................................36
DLL Calibrated DQS Delay and Control Block (DQSBUF)...........................................................................37
2.13. sysI/O Buffer......................................................................................................................................................39
2.13.1.
2.13.2.
Supported sysI/O Standards.....................................................................................................................39
sysI/O Banking Scheme ............................................................................................................................40
2.13.2.1. Typical sysI/O I/O Behavior During Power-up......................................................................................41
2.13.2.2. VREF1 and VREF2 .................................................................................................................................41
2.13.2.3. SysI/O Standards Supported by I/O Bank ............................................................................................41
2.13.2.4. Hot Socketing.......................................................................................................................................42
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FPGA-DS-02049-0.80
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