32-Bit System-on-Chip
LH7A404
Table 1. Functional Pin List (Cont’d)
OUTPUT
DRIVE
BGA
SIGNAL
DESCRIPTION
H2 COL0
H1 COL1
J4 COL2
J3 COL3
J2 COL4
J1 COL5
K4 COL6
K2 COL7
B1 TCLK
B2 TDO
Keyboard Interface
8 mA
JTAG Clock. This signal should be pulled-up to VDD
JTAG Data Out
4 mA
C1 TMST
C3 MEDCHG
D1 BATOK
JTAG Test Mode Select. This signal should be pulled-up to VDD
Media Change for Smart Card interface
Battery OK
D2 nBATCHG
G1 KMIDAT
H3 KMICLK
L9 BUZ
Battery Change
Keyboard / Mouse data
16 mA
16 mA
8 mA
Keyboard /Mouse clock
Buzzer Output (254 kHz MAX.)
Byte Lane Enable 2
AB7 nBLE2
Y8 nBLE1
16 mA
16 mA
Byte Lane Enable 1
AA12 BATCNTL
Battery Control for A/D controller battery monitor.
16 mA
N11 BOOTWIDTH0
N12 BOOTWIDTH1
Boot Width Pins. Used with the MEDCHG bit. On power up, the values on these pins are
latched to determine the width and type of Boot device. Boot width can be 8-, 16-, or 32-bit.
W12 LR_YM
AA13 AN1
Touch Screen Controller Lower Right Y-minus
A/D channel 1
Y13 AN6
A/D channel 6
W13 LL_YP
AB14 AN5
Touch Screen Controller Lower Left Y-plus
A/D channel 5
AA14 AN2
A/D channel 2
Y14 UR_XM
W14 AN4
Touch Screen Controller Upper Right X-minus
A/D channel 4
AB15 AN3
A/D channel 3
Y15 UL_XP
W16 nTEST0
Y17 nTEST1
AA22 OSCEN
C18 nCAS
D17 nRAS
A15 nBLE3
B15 nBLE0
C15 DQM0
D15 DQM1
A14 DQM2
B14 DQM3
B13 SCIIO
C13 SCICLK
D13 SCIRESET
A12 SCIVCCEN
Touch Screen Controller Upper Left X-plus,
Test Pins. Tie to VDD.
Oscillator Enable Output
Column Address Strobe Signal
Row Address Strobe Signal
Byte Lane Enable 3
8 mA
16 mA
16 mA
8 mA
Byte Lane Enable 0
8 mA
Data Mask for synchronous memories
16 mA
Smart Card Interface I/O
16 mA
16 mA
16 mA
16 mA
Smart Card Interface Clock
Smart Card Interface Reset
Smart Card Interface VCC Enable
Advance Data Sheet
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