LH7A404
32-Bit System-on-Chip
Table 1. Functional Pin List (Cont’d)
OUTPUT
DRIVE
BGA
SIGNAL
DESCRIPTION
H22 A16/SBANK0
H19 A17/SBANK1
G21 A18
Address Bus and Synchronous Bank 0
Address Bus and Synchronous Bank 1
16 mA
16 mA
F22 A19
F19 A20
E21 A21
E19 A22
Address Bus
16 mA
D21 A23
C21 A24
A18 A25
A17 A26
C17 A27
C14 nOE
Asynchronous Memory Output Enable
Asynchronous Memory Write Enable 0
Asynchronous Memory Controller Wait
Clock Enable 3 for Synchronous Memory
Synchronous Memory Clock2
16 mA
16 mA
A13 nWE0
M13 nWAIT
A16 SCKEN3
B16 SCLK
16 mA
24 mA
16 mA
16 mA
16 mA
16 mA
16 mA
16 mA
16 mA
C16 SCKE1
D16 SCKE0
A22 nSCS0
C20 nSCS1
A21 nSCS2
C19 nSCS3
A19 nSWE
Clock Enable 1 for Synchronous Memory
Clock Enable 0 for Synchronous Memory
Synchronous Memory Chip Select 0
Synchronous Memory Chip Select 1
Synchronous Memory Chip Select 2
Synchronous Memory Chip Select 3
Synchronous Memory Write Enable
M3 PA0/LCDVD16
M1 PA1/LCDVD17
N4 PA2
GPIO Port A and LCD data pins 16 and 17
8 mA
N3 PA3
N2 PA4
GPIO Port A
8 mA
N1 PA5
P4 PA6
P3 PA7
P2 PB0/UARTRXD1
L10 PB1/UARTTXD3
L11 PB2/UARTRXD3
M10 PB3/UARTCTS3
M11 PB4/UARTDCD3
N10 PB5/UARTDSR3
P1 PB6/BMISWIB/BMISMBIO
R1 PB7/BMISMBCLK
R2 PC0/TXD1
R3 PC1
GPIO Port B and UART1 Receive Data Input
GPIO Port B and UART3 Transmit Data Out
GPIO Port B and UART3 Receive Data In
GPIO Port B and UART3 Clear to Send
GPIO Port B and UART3 Data Carrier Detect
GPIO Port B and UART3 Data Set Ready
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
GPIO Port B and Battery Monitor Interface
8 mA
GPIO Port C and UART1 Transmit Data Output
16 mA
16 mA
16 mA
16 mA
16 mA
16 mA
16 mA
16 mA
GPIO Port C
GPIO Port C
GPIO Port C
GPIO Port C
GPIO Port C
GPIO Port C
GPIO Port C
T1 PC2
T2 PC3
T3 PC4
T4 PC5
U1 PC6
U2 PC7
6
Advance Data Sheet