Datasheet > LH5PV16256

LH5PV16256

更新时间： 2022-11-26 02:03:26

品牌	Logo	应用领域
夏普 - SHARP		/
页数	文件大小	规格书
14页	118K
描述
CMOS 4M (256K x 16) Pseudo-Static RAM

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LH5PV16256 数据手册

LH5PV16256

CMOS 4M (256 × 16) Pseudo-Static RAM

NOTES:

1. AC characteristics are measured at t_T= 5 ns.

2. AC characteristics are measured at the following condition:

3. Row address signals are latched in the memory at the falling edge of CE.

2.4 V

2.2 V

INPUT

0.8 V

0.4 V

2.0 V

OUTPUT

0.8 V

5PV16256S-13

Figure 3. AC Characteristics

4. Measured with a load equivalent to 50 pF.

5. Input data is latched in the memory at the earlier rising edge of CE and UWE/LWE. One of (t_AHW, t_DSW, t_DHW) and (t_AHC, t_DSC, t_DHC) needs

to be satisfied. The other is "Don’t care."

6. Address refresh or auto refresh is needed to be executed 2,048 times within 32 ms.

In order to initialize the internal circuits, an initial pause of 500 µs with CE = RFSH = V_IHis required after power-up, and followed by at

least 8 dummy cycles. When supply voltage falls down below the recommended supply voltage by temporarily power-down, a waiting time

is required at V_CC= 0 V for more than 400 ms before power-up, and a pause of 500 µs with CE = RFSH = V_IHand 8 dummy cycles are

also necessary after power-up.

8. Auto refresh and self refresh are defined by RFSH pulse width during CE = V_IH. If RFSH pulse width is shorter than t_FAP(MAX.), the cycle

is an auto refresh cycle and memory cells are refreshed by an internal counter. If RFSH pulse width is longer than t_FAS(MIN.), the cycle

is a self refresh cycle and memory cells are refreshed by an internal clock generator automatically.

9. t_RCHand t_WHZare determined by the earlier falling edge of UWE and LWE.

10. t_WCSis determined by the later falling edge of UWE and LWE.

11. t_RCS, t_WLZ, and t_DHWare determined by the later rising edge of UWE and LWE.

12. t_WCHand t_DSWare determined by the earlier rising edge of UWE and LWE.

13. t_WHZ, t_WCP, t_WCS, t_WCH, t_DSW, t_DHW, t_WLZ, and t_AHWshould be satisfied by both UWE and LWE.

14. The transition time of the supply voltage in data retention mode is less than 0.05 V/ms.

15. The width of data retention period is more than t_FAS(MIN.) like self-refresh cycle.

16. All input pins are required to be higher than -0.3 V.

17. RFSH must be lower than 0.2 V during the data retention period.

18. CE and CS must be higher than V_CC- 0.2 V during the data retention period.

1...3 4 567 8 9...14

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