Datasheet > 存储 > 闪存> LH28F160BGH-TL

LH28F160BGH-TL

更新时间： 2024-01-06 11:14:42

品牌	Logo	应用领域
夏普 - SHARP		闪存
页数	文件大小	规格书
36页	225K
描述
16 M-bit (1 MB x 16) Smart 3 Flash Memories

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技术参数
数据手册

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LH28F160BGH-TL 技术参数

生命周期：	Obsolete	包装说明：	SOP-44
Reach Compliance Code：	unknown	风险等级：	5.76
最长访问时间：	100 ns	其他特性：	USER CONFIGURABLE AS 1M X 16
JESD-30 代码：	R-PDSO-G44	长度：	28.2 mm
内存密度：	16777216 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	44	字数：	2097152 words
字数代码：	2000000	工作模式：	ASYNCHRONOUS
组织：	2MX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	PARALLEL
编程电压：	3 V	认证状态：	Not Qualified
座面最大高度：	3.15 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	类型：	NOR TYPE
宽度：	13.2 mm	Base Number Matches：	1

LH28F160BGH-TL 数据手册

LH28F160BG-TL/BGH-TL

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses

are internally latched during a write cycle.

A0-A19

INPUT

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs

data during memory array, status register and identifier code read cycles. Data pins float

to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle.

INPUT/

DQ0-DQ15

CE#

OUTPUT

CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense

amplifiers. CE#-high deselects the device and reduces power consumption to standby

levels.

INPUT

RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets

internal automation. RP#-high enables normal operation. When driven low, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep

power-down sets the device to read array mode. Block erase or word write with VIH <

RP# < VHH produce spurious results and should not be attempted.

OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

RP#

OE#

WE#

INPUT

WRITE PROTECT : Master control for boot blocks locking. When VIL, locked boot

blocks cannot be erased and programmed.

WP#

INPUT

READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is

performing an internal operation (block erase or word write). RY/BY#-high-impedance

indicates that the WSM is ready for new commands, block erase is suspended, and

word write is inactive, word write is suspended, or the device is in deep power-down

mode.

RY/BY#

OUTPUT

BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or

writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase and

word write with an invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce

spurious results and should not be attempted.

VPP

VCC

SUPPLY

DEVICE POWER SUPPLY : 2.7 to 3.6 V. Do not float any power pins. With VCC ≤

VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid

VCC voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results

and should not be attempted.

GND

SUPPLY GROUND : Do not float any ground pins.

NO CONNECT : Lead is not internal connected; recommend to be floated.

- 4 -

1 2 345 6 7...36

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LH28F160BGR-BTL10	SHARP	Flash, 1MX16, 100ns, PDSO48, REVERSE, TSOP1-48	获取价格
LH28F160BGR-BTL12	SHARP	Flash, 1MX16, 120ns, PDSO48, REVERSE, TSOP1-48	获取价格
LH28F160BGR-TTL12	SHARP	Flash, 1MX16, 120ns, PDSO48, REVERSE, TSOP1-48	获取价格
LH28F160BG-TL	SHARP	16 M-bit (1 MB x 16) Smart 3 Flash Memories	获取价格
LH28F160BHE-TTL90	SHARP	16M (x8/x16) Flash Memory	获取价格
LH28F160BJB-BTL90	ETC	Flash ROM	获取价格

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