LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
registered output port for the lower
twelve bits of the 16-bit Filter B
output.
LDB must be set HIGH immediately
ACCA — Accumulator A Control
after power up to ensure proper oper-
ation of the input circuitry (see the
LF InterfaceTM section for a full discus-
sion).
When ACCA is HIGH, Accumulator
A is enabled for accumulation and the
Accumulator A Output Register is dis-
abled for loading. When ACCA is
LOW, no accumulation is performed
and the Accumulator A Output Regis-
ter is enabled for loading. ACCA is
latched on the rising edge of CLK.
ROUT11-0 — Reverse Cascade Output
In Single Filter Mode, ROUT11-0 is
a 12-bit registered cascade output
port. ROUT11-0 on one device should
be connected to RIN11-0 of another
LF3320. In Dual Filter Mode, ROUT3-0
is a 4-bit registered output port for
the upper four bits of the 16-bit Filter
B output. In this mode, ROUT11-4 is
disabled.
CENB — Coefficient Address Enable B
When CENB is LOW, data on CAB7-0
is latched into Coefficient Address
Register B on the rising edge of CLK.
When CENB is HIGH, data on CAB7-0
is not latched and the register’s con-
tents will not be changed.
ACCB — Accumulator B Control
When ACCB is HIGH, Accumulator B
is enabled for accumulation and the
Accumulator B Output Register is dis-
abled for loading. When ACCB is
LOW, no accumulation is performed
and the Accumulator B Output Regis-
ter is enabled for loading. ACCB is
latched on the rising edge of CLK.
TXFRA — Filter A LIFO Transfer
Control
Controls
LDA — Coefficient A Load
TXFRA is used to change which LIFO
in the data reversal circuitry sends
data to the reverse data path and
which LIFO receives data from the
forward data path in Filter A. When
TXFRA goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the for-
ward data path, and the LIFO receiv-
ing data from the forward data path
becomes the LIFO sending data to
the reverse data path. The device
must see a HIGH to LOW transition
of TXFRA in order to switch LIFOs.
TXFRA is latched on the rising edge
of CLK.
When LDA is LOW, data on CFA11-0
is latched into the Filter A LF Inter-
faceTM on the rising edge of CLK.
When LDA is HIGH, data is not
SHENA — Filter A Shift Enable
loaded into the Filter A LF InterfaceTM
When enabling the LF InterfaceTM for
.
In Dual Filter Mode, SHENA enables
or disables the loading of data into the
Input (DIN11-0) and Filter A I/D Reg-
isters. When SHENA is LOW, data
is latched into the Input/Cascade Reg-
isters and shifted through the I/D
Registers on the rising edge of CLK.
When SHENA is HIGH, data can
not be loaded into the Input/Cascade
Registers or shifted through the I/D
Registers and their contents will not
be changed.
data input, a HIGH to LOW transition
of LDA is required in order for the
input circuitry to function properly.
Therefore, LDA must be set HIGH
immediately after power up to ensure
proper operation of the input circuitry
(see the LF InterfaceTM section for a
full discussion).
CENA — Coefficient Address Enable A
TXFRB — Filter B LIFO Transfer
Control
When CENA is LOW, data on CAA7-0
is latched into Coefficient Address
Register A on the rising edge of
CLK. When CENA is HIGH, data on
CAA7-0 is not latched and the regis-
ter’s contents will not be changed.
In Single Filter Mode, SHENA also
enables or disables the loading of
data into the Reverse Cascade Input
(RIN11-0), Cascade Output
(COUT11-0), Reverse Cascade Output
(ROUT11-0) and Filter B I/D Registers.
It is important to note that in Single
Filter Mode, both SHENA and SHENB
should be connected together. Both
must be active to enable data loading
in Single Filter Mode. SHENA is
latched on the rising edge of CLK.
TXFRB is used to change which LIFO
in the data reversal circuitry sends
data to the reverse data path and
which LIFO receives data from the
forward data path in Filter B. When
TXFRB goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the for-
ward data path, and the LIFO receiv-
ing data from the forward data path
becomes the LIFO sending data to
the reverse data path. The device
must see a HIGH to LOW transition
of TXFRB in order to switch LIFOs.
TXFRB is latched on the rising edge of
CLK.
LDB — Coefficient B Load
When LDB is LOW, data on CFB11-0 is
latched into the Filter B LF InterfaceTM
on the rising edge of CLK. When LDB
is HIGH, data is not loaded into the
Filter B LF InterfaceTM. When enabling
the LF InterfaceTM for data input, a
HIGH to LOW transition of LDB is
required in order for the input cir-
cuitry to function properly. Therefore,
SHENB — Filter B Shift Enable
In Dual Filter Mode, SHENB enables
or disables the loading of data into
the Reverse Cascade Input (RIN11-0),
Video Imaging Products
6/22/2007–LDS.3320-R
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