Datasheet > LF198QML-SP

LF198QML-SP

更新时间： 2022-10-12 16:15:22

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
20页	994K
描述
Monolithic Sample-and-Hold Circuits

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

LF198QML-SP 数据手册

Typical Applications (Continued)

Differential Hold

Capacitor Hysteresis Compensation

20122256

20122257

**Adjust for amplitude

Hold Settling Time: The time required for the output to

settle within 1 mV of final value after the “hold” logic com-

mand.

Definition of Terms

Hold Step: The voltage step at the output of the sample and

hold when switching from sample mode to hold mode with a

steady (dc) analog input voltage. Logic swing is 5V.

Dynamic Sampling Error: The error introduced into the

held output due to a changing analog input at the time the

hold command is given. Error is expressed in mV with a

given hold capacitor value and input slew rate. Note that this

error term occurs even for long sample times.

Acquisition Time: The time required to acquire a new ana-

log input voltage with an output step of 10V. Note that

acquisition time is not just the time required for the output to

settle, but also includes the time required for all internal

nodes to settle so that the output assumes the proper value

when switched to the hold mode.

Aperture Time: The delay required between “Hold” com-

mand and an input analog transition, so that the transition

does not affect the held output.

Gain Error: The ratio of output voltage swing to input volt-

age swing in the sample mode expressed as a per cent

difference.

www.national.com

中文翻译

下载PDF

型号	品牌	描述	获取价格	数据表
LF198WG/883	TI	LF198QML Monolithic Sample-and-Hold Circuits	获取价格
LF198WG-MLS	NSC	SAMPLE AND HOLD AMPLIFIER, 20us ACQUISITION TIME, CDSO14, CERAMIC, SOIC-14	获取价格
LF198WG-QMLV	TI	LF198QML Monolithic Sample-and-Hold Circuits	获取价格
LF1OX	ETC	PATCHCORD 1/4" ORANGE 1FT	获取价格
LF1PX	ETC	PATCHCORD 1/4" PURPLE 1FT	获取价格
LF1RX	ETC	PATCHCORD 1/4" RED 1FT	获取价格