Datasheet > LD3985G24R

LD3985G24R

更新时间： 2024-01-15 16:13:27

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		稳压器信息通信管理
页数	文件大小	规格书
14页	396K
描述
ULTRA LOW DROP-LOW NOISE BICMOS VOLTAGE REGULATORS LOW ESR CAPACITORS COMPATIBLE

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LD3985G24R 数据手册

LD3985 SERIES

Figure 2: Connection Diagram (top view for SOT and TSOT, top through view for Flip-Chip)

TSOT23-5L/SOT23-5L

Flip-Chip

Table 4: Pin Description

Pin N°

SOT23-5L/

TSOT23-5L

Pin N°

Flip-Chip

Symbol

Name and Function

Input Voltage of the LDO

Common Ground

GND

Inhibit Input Voltage: ON MODE when V

≥ 1.2V, OFF MODE when V

≤

INH

0.4V (Do not leave floating, not internally pulled down/up)

BYPASS

Bypass Pin: Connect an external capacitor (usually 10nF) to minimize noise

voltage

Output Voltage of the LDO

Figure 3: Typical Application Circuit

3/14

1 234 5 6 7...14

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