LAN9221/LAN9221i
High-Performance 16-bit Non-PCI
10/100 Ethernet Controller with
Variable Voltage I/O
Datasheet
PRODUCT FEATURES
Single chip Ethernet controller
Highlights
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Fully compliant with IEEE 802.3/802.3u standards
Optimized for high performance applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and Half-duplex support
Full-duplex flow control
1.8V to 3.3V variable voltage I/O accommodates wide
range of I/O signalling without voltage level shifters
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
Integrated PHY with HP Auto-MDIX support
Integrated checksum offload engine helps reduce
CPU load
Flexible address filtering modes
Low pin count and small body size package for small
form factor system designs
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One 48-bit perfect address
64 hash-filtered multicast addresses
Pass all multicast
Promiscuous mode
Inverse filtering
Target Applications
Cable, satellite, and IP set-top boxes
Digital video recorders and DVD recorder/players
Digital TV
Pass all incoming with status report
Disable reception of broadcast packets
Integrated 10/100 Ethernet PHY
Digital media clients/servers and home gateways
Video-over IP solutions, IP PBX & video phones
Wireless routers & access points
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Supports HP Auto-MDIX
Auto-negotiation
Supports energy-detect power down
High-end audio distribution systems
Host bus interface
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Simple, SRAM-like interface
16-bit data bus
16Kbyte FIFO with flexible TX/RX allocation
One configurable host interrupt
Key Benefits
Non-PCI Ethernet controller for high performance
applications
Miscellaneous features
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16-bit interface with fast bus cycle times
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Burst-mode read support
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Small form factor, 56-pin QFN lead-free RoHS
Compliant package
Integrated 1.8V regulator
Integrated checksum offload engine
Mixed endian support
General Purpose Timer
Optional EEPROM interface
Support for 3 status LEDs multiplexed with
Programmable GPIO signals
Minimizes dropped packets
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Internal buffer memory can store over 200 packets
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Automatic PAUSE and back-pressure flow control
Minimizes CPU overhead
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Supports Slave-DMA
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Interrupt Pin with Programmable Hold-off timer
Reduces system cost and increases design flexibility
SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
Single 3.3V Power Supply with Variable Voltage I/O
Commercial and Industrial Temperature Support
Reduced Power Modes
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Numerous power management modes
Wake on LAN
Magic packet wakeup
Wakeup indicator event signal
Link Status Change
SMSC LAN9221/LAN9221i
DATASHEET
Revision 2.6 (12-04-08)