L7C108
L7C109
128K x 8 Static RAM
Pin Configuration
FEATURES
128K x 8 Static RAM with Chip
32-pin Ceramic DIP
32-pin Ceramic SOJ
Select Powerdown, Output Enable
and Single or Dual Chip Selects
32-pin Quad CLCC
32-pin Ceramic LCC
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
V
A
CE
CC
15
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
V
A
CE
WE
CC
15
A
A
A
16
14
12
A16
A14
A12
4
3
2
1
32 31 30
29
2
2
WE
5
6
7
8
9
A7
A6
A5
A4
A3
WE
A13
A8
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
1
2
3
A
A
A
A
OE
A10
CE
DQ
DQ
DQ
DQ
DQ
13
8
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
1
2
3
A
A
A
A
13
Data Retention at 2 V for Battery
Backup Operation
28
27
26
25
24
23
22
21
8
9
9
A9
11
Top
View
11
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
A11
OE
A10
CE1
DQ8
9
9
OE
A10
A2 10
A1 11
A0 12
10
11
12
13
14
15
16
10
11
12
13
14
15
16
Package Styles Available:
CE
DQ
DQ
DQ
DQ
DQ
8
7
6
5
4
8
7
6
5
4
ꢀ
ꢀ
ꢀ
ꢀ
xꢀꢁꢂꢃSLQꢀ&HUDPLFꢀꢄꢅꢅPLOꢀ',3ꢆꢇ'ꢈꢂꢉ
xꢀꢁꢂꢃSLQꢀ&HUDPLFꢀ/&&ꢆꢇ.ꢈꢈꢉ
xꢀꢁꢂꢃSLQꢀ&HUDPLFꢀ62-ꢆꢇ<ꢈꢉ
DQ1 13
DQ
DQ
DQ
DQ
DQ
DQ
14 15 16 17 18 19 20
VSS
VSS
xꢀꢁꢂꢃSLQꢀ4XDGꢀ&HUDPLFꢀ/&&ꢆꢇ.$ꢈꢉ
OVERVIEW
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
&KLSꢀ (QDEOHVꢀ ꢆRQHꢀ DFWLYHꢃORZꢉꢊꢀ ꢀ 7KHVHꢀ
devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
Memory locations are specified on
address pins A0 through A16. For the
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE1 and OE
LOW while WE remains HIGH. For the
L7C109, CE1 and OE must be LOW
while CE2 and WE are HIGH.The data in
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE1 or OE is
HIGH, or CE2ꢀꢆ/ꢌ&ꢈꢅꢍꢉꢀRUꢀ:(ꢀLVꢀ/2:ꢊ
Writing to an addressed location is
accomplished when the active-low CE1
and WE inputs are both LOW, and CE2
ꢆ/ꢌ&ꢈꢅꢍꢉꢀLVꢀ+,*+ꢊꢀꢀ$Q\ꢀRIꢀWKHVHꢀVLJQDOVꢀ
Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
ꢆꢃ/ꢀ 9HUVLRQꢉꢀ DWꢀ ꢈꢋꢀ QVꢊꢀ ꢀ 'DWDꢀ PD\ꢀ EHꢀ
retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
FKURQRXVꢀ ꢆXQFORFNHGꢉꢀ RSHUDWLRQꢀ ZLWKꢀ
matching access and cycle times. The
1M Static RAMs
LOGIC Devices Incorporated
www.logicdevices.com
1
Feb 17, 2012 LDS-L7C108/9-G
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
