Datasheet > L29C525PC20

L29C525PC20

更新时间： 2024-09-27 23:43:39

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
6页	166K
描述
Pipeline Register

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L29C525PC20 数据手册

L29C525

DEVICES INCORPORATED

Dual Pipeline Register

L29C525

Dual Pipeline Register

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The L29C525 is a high-speed, low

power CMOS pipeline register. It is

Instruction I1-0 = 01 (Push B) acts

similarly to the Push A and B

pin-for-pin compatible with the AMD instruction, except that only the B side

Am29525. The L29C525 can be registers are shifted. The input data is

configured as two independent 8-level applied to register B0, and the

❑ Dual 8-Deep Pipeline Register

❑ Configurable to Single 16-Deep

❑ Low Power CMOS Technology

❑ Replaces AMD Am29525

❑ Load, Shift, and Hold Instructions

❑ Separate Data In and Data Out Pins

❑ Three-State Outputs

pipelines or as a single 16-level

contents of register B7 are lost. The

contents of the A side registers are

unaffected. Instruction I1-0 = 10 (Push

A) is identical to the Push B

instruction, except that the A side

registers are shifted and the B side

registers are unaffected.

pipeline. The configuration imple-

mented is determined by the instruc-

tion code (I1-0) as shown in Table 2.

❑ Package Styles Available:

• 28-pin Plastic DIP

The I1-0 instruction code controls the

internal routing of data and loading of

each register. For instruction I1-0 = 00

(Push A and B), data applied at the

D7-0 inputs is latched into register A0

on the rising edge of CLK. The

contents of A0 simultaneously move

to register A1, A1 moves to A2, and so

on. The contents of register A7 are

wrapped back to register B0. The

registers on the B side are similarly

shifted, with the contents of register

B7 lost.

• 28-pin Plastic LCC, J-Lead

Instruction I1-0 = 11 (Hold) causes no

internal data movement. It is equiva-

lent to preventing the application of a

clock edge to any internal register.

The contents of any of the registers is

selectable at the output through the

use of the S3-0 control inputs. The

independence of the I and S control

lines allows simultaneous reading and

writing. Encoding for the S3-0 controls

is given in Table 3.

L29C525 BLOCK DIAGRAM

7-0

1-0

CLK

7-0

3-0

Pipeline Registers

03/32/2000–LDS.29C525-G

12 3 4 5 6

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与L29C525PC20相关器件

型号	品牌	获取价格	描述	数据表
L29C818CC15	ETC	获取价格	Pipeline Register
L29C818CC25	ETC	获取价格	Pipeline Register
L29C818CM24	ETC	获取价格	Pipeline Register
L29C818CM30	ETC	获取价格	Pipeline Register
L29C818CMB24	ETC	获取价格	Pipeline Register
L29C818CMB30	ETC	获取价格	Pipeline Register
L29C818DC25	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-24
L29C818DM30	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-24
L29C818DMB24	ETC	获取价格	Pipeline Register
L29C818DMB30	LOGIC	获取价格	Pipeline Register, 8-Bit, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, HERMETIC SEALED, DIP-28