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L29C818KMB30 PDF预览

L29C818KMB30

更新时间： 2024-09-29 20:21:11
品牌 Logo 应用领域
逻辑 - LOGIC 外围集成电路
页数 文件大小 规格书
10页 105K
描述
Pipeline Register, 8-Bit, CMOS, CQCC28, 0.450 X 0.450 INCH, CERAMIC, LCC-28

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L29C818KMB30 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：QCCN, LCC28,.45SQ
针数：28Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
其他特性：ICC SPECIFIED @ 5MHZ边界扫描：NO
外部数据总线宽度：8JESD-30 代码：S-CQCC-N28
JESD-609代码：e0长度：11.4935 mm
低功率模式：NO湿度敏感等级：3
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出数据总线宽度：8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装等效代码：LCC28,.45SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：5 V认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：2.54 mm
子类别：DSP Peripherals最大压摆率：15 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：11.4935 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, PIPELINE REGISTERBase Number Matches：1

L29C818KMB30 数据手册

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L29C818  
8-bit Serial Scan Shadow Register  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The L29C818 is a high-speed octal  
register designed especially for  
Also, data present on the SDI pin is  
loaded into the least significant  
❑ Octal Register with Additional 8-bit  
Shiftable Shadow Register  
applications using serial-scan diagnos- position of the S register on the rising  
❑ Serial Load/ Verify of Writable  
tics or writable control store. It is pin  
and functionally compatible with the  
AMD Am29818 bipolar device.  
edge of CLK S. In this mode, the S  
register performs a right-shift opera-  
tion with the contents of each bit  
position replaced by the value in the  
next least significant location. The  
value in S7 is shifted out on the serial  
data output (SDO) pin. The SDI and  
SDO pins allow serial connection of  
multiple L29C818 devices into a  
diagnostic loop. When MODE is  
LOW, the operation of the P and S  
registers are completely independent  
and no timing relationship is enforced  
between CLK P and CLK S.  
Control Store RAM  
❑ Serial Stimulus/ Observation of  
Sequential Logic  
❑ High-Speed, Low Power CMOS  
The L29C818 consists of an octal  
register, the P register, internally  
connected to an 8-bit shift register, the  
S register. Each has its own corres-  
ponding clock pin and the P register  
has a three-state output control.  
Technology  
❑ Replaces AMD Am29818  
❑ DECC SMD No. 5962-90515  
❑ Available 100% Screened to  
MIL-STD-883, Class B  
An input control signal, MODE, in  
combination with the S register serial  
data input (SDI) pin controls data  
routing within the L29C818. When  
the MODE input is LOW, indicating  
normal operation, data present on the  
D7-0 pins is loaded into the P register  
on the rising edge of CLK P. The  
contents of the P register are visible on  
the output pins Y7-0 when the OE  
control line is LOW.  
❑ Package Styles Available:  
• 24-pin Plastic DIP  
• 24-pin Sidebraze, Hermetic DIP  
• 28-pin Ceramic LCC  
When MODE is HIGH, the internal  
multiplexers route data between the S  
and P registers and the Y port. The  
contents of the S register are loaded  
into the P register on the rising edge of  
L29C818 BLOCK DIAGRAM  
SDI  
SDO  
CLK S  
MODE  
S REGISTER  
S7-0  
Y0  
Y1  
Y7  
SDI  
D7-0  
SDO  
8
8
8
MODE  
D Q  
D
D
D
EN  
EN  
EN  
MUX  
8
CLK S  
Q
Q
Q
CLK P  
OE  
P REGISTER  
S0  
S1  
S7  
8
P7-0  
OBSOLETE  
S REGISTER  
8
Y7-0  
Shadow Registers  
03/04/99–LDS.818-L  
1
1234567...10

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