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KSZ8775CLXCC

更新时间: 2022-02-26 12:18:03
品牌 Logo 应用领域
美国微芯 - MICROCHIP 局域网(LAN)标准
页数 文件大小 规格书
132页 1384K
描述
Integrated 5–Port 10/100 Managed Ethernet Switch with Port 4 RMII and Port 5 RGMII/MII/RMII Interfaces

KSZ8775CLXCC 数据手册

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KSZ8775CLX  
Integrated 5–Port 10/100 Managed Ethernet  
Switch with Port 4 RMII and Port 5 RGMII/MII/  
RMII Interfaces  
- Supports reduced media independent inter-  
face (RMII) with 50 MHz reference clock out-  
put  
Features  
• Management Capabilities  
- The KSZ8775CLX includes all the functions  
of a 10/100BASE-T/TX switch system, which  
combines a switch engine, frame buffer  
management, address look-up table, queue  
management, MIB counters, media access  
controllers (MAC), and PHY transceivers  
- Supports media independent interface (MII)  
in either PHY mode or MAC mode on Port 5  
- LinkMD® cable diagnostic capabilities for  
determining cable opens, shorts, and length  
• Advanced Switch Capabilities  
- Non-blocking store-and-forward switch fabric  
assures fast packet delivery by utilizing a  
1024-entry forwarding table  
- Non-blocking store-and-forward switch fabric  
assures fast packet delivery by utilizing a  
1024-entry forwarding table  
- 64kb frame buffer RAM  
- Port mirroring/monitoring/sniffing: ingress  
and/or egress traffic to any port  
- IEEE 802.1q VLAN support for up to 128  
active VLAN groups (full-range 4096 of VLAN  
IDs)  
- MIB counters for fully compliant statistics  
gathering - 36 counters per port  
- IEEE 802.1p/q tag insertion or removal on a  
per port basis (egress)  
- Hardware support for port-based flush and  
freeze command in MIB counter.  
- VLAN ID tag/untag options on per port basis  
- Multiple loopback of remote, PHY, and MAC  
modes support for the diagnostics  
- Fully compliant with IEEE 802.3/802.3u stan-  
dards  
- Rapid spanning tree support (RSTP) for  
topology management and ring/linear  
recovery  
- IEEE 802.3x full-duplex with force mode  
option and half-duplex back-pressure colli-  
sion flow control  
• Robust PHY Ports  
- IEEE 802.1w rapid spanning tree protocol  
support  
- Four integrated IEEE 802.3/802.3u-compliant  
Ethernet transceivers supporting 10Base-T  
and 100BASE-TX  
- IGMP v1/v2/v3 snooping for multicast packet  
filtering  
- 802.1az EEE supported  
- QoS/CoS packets prioritization support:  
802.1p, DiffServ-based and re-mapping of  
802.1p priority field per port basis on four  
priority levels  
- On-chip termination resistors and internal  
biasing for differential pairs to reduce power  
- HP Auto MDI/MDI-X™ crossover support  
eliminates the need to differentiate between  
straight or crossover cables in applications  
- IPv4/IPv6 QoS support  
- IPv6 multicast listener discovery (MLD)  
snooping  
• MAC and GMAC Ports  
- Four internal media access control (MAC1 to  
MAC4) units and one internal Gigabit media  
access control (GMAC5) unit  
- Programmable rate limiting at the ingress and  
egress ports on a per port basis  
- Jitter-free per-packet-based rate limiting  
support  
- RGMII, MII, or RMII interfaces support for the  
Port 5 GMAC5 with uplink and RMII interface  
for Port 4 MAC4  
- Tail tagging mode (one byte added before  
FCS) support on Port 5 to inform the proces-  
sor which ingress port receives the packet  
and its priority  
- 2 kb jumbo packet support  
- Tail tagging mode (one byte added before  
FCS) support on Port 5 to inform the  
processor which ingress port receives the  
packet and its priority  
- Broadcast storm protection with percentage  
control (global and per port basis)  
DS00002129C-page 1  
2015 Microchip Technology Inc.  

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