KSZ8721B

更新时间： 2024-02-11 09:08:58

品牌	Logo	应用领域
麦瑞 - MICREL		局域网（LAN）标准
页数	文件大小	规格书
32页	201K
描述
2.5V 10/100BasTX/FX MII Physical Layer Transceiver

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技术参数
数据手册

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KSZ8721B 技术参数

生命周期：	Not Recommended	包装说明：	SSOP,
Reach Compliance Code：	unknown	风险等级：	5.71
JESD-30 代码：	R-PDSO-G48	长度：	15.875 mm
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
筛选级别：	TS 16949	座面最大高度：	2.794 mm
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ETHERNET TRANSCEIVER
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.493 mm	Base Number Matches：	1

KSZ8721B 数据手册

KS8721B/BT

Micrel

Pin Description

Pin Number

Pin Name

Type^{(Note 1)}

Pin Function

MDIO

MDC

I/O

Management Interface (MII) Data I/O: This pin requires an external 10K pull-up

resistor.

Management Interface (MII) Clock Input: This pin is synchronous to the MDIO

data interface

RXD3/

PHYAD1

Ipd/O

MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.

When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.

RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is

latched as PHYADDR [1] during reset. See “Strapping Options” section for

details.

RXD2/

PHYAD2

Ipd/O

MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]

during reset. See “Strapping Options” section for details.

RXD1/

PHYAD3

MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]

during reset. See “Strapping Options” section for details.

RXD0/

PHYAD4

MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]

during reset. See “Strapping Options” section for details.

VDDIO

GND

Pwr

GND

Ipd/O

Digital IO 2.5 /3.3V tolerance power supply.

Ground.

RXDV/

CRSDV/

MII Receive Data Valid Output: The pull-up/pull-down value is latched as

pcs_lpbk during reset. See “Strapping Options” section for details.

PCS_LPBK

RXC

MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.

RXER/ISO

Ipd/O

MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE

during reset. See “Strapping Options” section for details.

GND

VDDC

TXER

GND

Pwr

Ground.

Digital core 2.5V only power supply.

MII Transmit Error Input.

Ipd

TXC/

Ipu/O

MII Transmit Clock Output: RMII Reference Clock Input.

REFCLK

TXEN

TXD0

Ipd

MII Transmit Enable Input

MII Transmit Data Input

TXD1

Ipd

TXD2

Ipd

TXD3

Ipd

COL/RMII

Ipd/O

MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select

during reset. See “Strapping Options” section for details.

VDDIO

Pwr

Digital IO 2.5/3.3V tolerance power supply.

Note 1. Pwr = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Gnd = ground

Ipu = input w/ internal pull-up

Ipd = input w/ internal pull-down

Ipd/O = input w/ internal pull-down during reset, output pin otherwise

Ipu/O = input w/ internal pull-up during reset, output pin otherwise

PU = strap pin pull-up

PD = strap pin pull-down

NC = No connect

KS8721B/BT

August 2003

1...3 4 567 8 9...32

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与KSZ8721B相关器件

型号	品牌	描述	获取价格	数据表
KSZ8721BI	MICREL	2.5V 10/100BasTX/FX MII Physical Layer Transceiver	获取价格
KSZ8721BI	MICROCHIP	DATACOM, ETHERNET TRANSCEIVER, PDSO48	获取价格
KSZ8721BITR	MICREL	暂无描述	获取价格
KSZ8721BI-TR	MICROCHIP	DATACOM, ETHERNET TRANSCEIVER, PDSO48	获取价格
KSZ8721BL	MICREL	3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver	获取价格
KSZ8721BL	MICROCHIP	DATACOM, ETHERNET TRANSCEIVER, PQFP48	获取价格

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