Datasheet > KAD5512P-12

KAD5512P-12

更新时间： 2023-12-20 18:44:45

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
36页	1796K
描述
12-Bit, 125MSPS Single-Channel ADC with LVDS/LVCMOS Outputs

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KAD5512P-12 数据手册

KAD5512P

Pin Configuration

KAD5512P

(48 LD QFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

AVDD

DNC

AVSS

VINN

D4P

D4N

D3P

D3N

CLKOUTP

CLKOUTN

RLVDS

OVSS

PAD

VINP

AVSS

AVDD

28 D2P

D2N

VCM

26 D1P

D1N

DNC 11

AVSS

CONNECT THERMAL PAD TO AVSS

13 14 15 16 17 18 19 20 21 22 23 24

FIGURE 3. PIN CONFIGURATION

Pin Descriptions - 48 Ld QFN

PIN NUMBER

LVDS [LVCMOS] NAME

LVDS [LVCMOS] FUNCTION

1, 9, 13, 17, 47

AVDD

1.8V Analog Supply

Do Not Connect

Analog Ground

2, 3, 4, 11, 21, 22

DNC

5, 8, 12, 48

6, 7

AVSS

VINN, VINP

VCM

Analog Input Negative, Positive

Common-Mode Output

14, 15

CLKP, CLKN

NAPSLP

RESETN

OVSS

Clock Input True, Complement

Tri-Level Power Control (Nap, Sleep modes)

Power On Reset (Active Low, see page 19)

Output Ground

19, 29, 42

20, 37

OVDD

1.8V Output Supply

D0N

[NC]

LVDS DDR Logical Bits 1, 0 Output Complement

[NC in LVCMOS]

FN6807 Rev 5.00

May 31, 2016

Page 7 of 36

1...4 5 678 9 10...36

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