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K4S283233E-DG1L PDF预览

K4S283233E-DG1L

更新时间: 2023-06-15 00:00:00
品牌 Logo 应用领域
三星 - SAMSUNG 时钟动态存储器内存集成电路
页数 文件大小 规格书
10页 81K
描述
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90

K4S283233E-DG1L 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.75
最长访问时间:7 ns最大时钟频率 (fCLK):105 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PBGA-B90内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:32
端子数量:90字数:4194304 words
字数代码:4000000最高工作温度:85 °C
最低工作温度:-25 °C组织:4MX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA90,9X15,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, FINE PITCH
电源:3/3.3 V认证状态:Not Qualified
刷新周期:4096连续突发长度:1,2,4,8,FP
最大待机电流:0.0005 A子类别:DRAMs
最大压摆率:0.13 mA表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOMBase Number Matches:1

K4S283233E-DG1L 数据手册

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K4S283233E-S(D)E/N/G/C/L/F  
Mobile-SDRAM  
1M x 32Bit x 4 Banks SDRAM in 90FBGA  
FEATURES  
GENERAL DESCRIPTION  
The K4S283233E is 134,217,728 bits synchronous high data  
rate Dynamic RAM organized as 4 x 1,048,576 words by 32  
bits, fabricated with SAMSUNG¢s high performance CMOS  
technology. Synchronous design allows precise cycle control  
with the use of system clock and I/O transactions are possible  
on every clock cycle. Range of operating frequencies, program-  
mable burst lengths and programmable latencies allow the  
same device to be useful for a variety of high bandwidth and  
high performance memory system applications.  
• 3.0V & 3.3V power supply  
• LVCMOS compatible with multiplexed address  
• Four banks operation  
• MRS cycle with address key programs  
-. CAS latency (1, 2 & 3)  
-. Burst length (1, 2, 4, 8 & Full page)  
-. Burst type (Sequential & Interleave)  
• EMRS cycle with address key programs.  
-. PASR(Partial Array Self Refresh)  
-. Internal TCSR(Temperature Compensated Self Refresh)  
• All inputs are sampled at the positive going edge of the system  
clock  
ORDERING INFORMATION  
Part No.  
Max Freq.  
Interface Package  
• Burst read single-bit write operation  
• DQM for masking  
K4S283233E-S(D)E/N/G/C/L/F60 166MHz(CL=3)  
133MHz(CL=3)  
K4S283233E-S(D)E/N/G/C/L/F75  
105MHz(CL=2)  
90FBGA  
• Auto & self refresh  
LVCMOS  
Pb  
• 64ms refresh period (4K cycle).  
K4S283233E-S(D)E/N/G/C/L/F1H 105MHz(CL=2)  
(Pb Free)  
• Extended Temperature Operation (-25°C ~ 85°C).  
• Commercial Temperature Operation (-25°C ~ 70°C).  
• 90Balls Monolithic FBGA(11mm x 13mm)  
• Pb for -SXXX, Pb Free for -DXXX.  
*1  
K4S283233E-S(D)E/N/G/C/L/F1L  
105MHz(CL=3)  
- S(D)E/N/G : Normal/Low Power, Extended Temperature.  
- S(D)C/L/F : Normal/Low Power, Commercial Temperature.  
Note :  
1. In case of 40MHz Frequency, CL1 can be supported.  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
1M x 32  
1M x 32  
1M x 32  
1M x 32  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
DQM  
* Samsung Electronics reserves the right to change products or specification without notice.  
May. 2003  

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