K4E660812D,K4E640812D
CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A12]
Symbol
CIN1
Min
Max
Units
pF
-
-
-
5
7
7
Input capacitance [RAS, CAS, W, OE]
Output capacitance [DQ0 - DQ7]
CIN2
pF
CDQ
pF
AC CHARACTERISTICS (0°C£TA£70°C, See note 2)
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
-45
-50
-60
Parameter
Symbol
Units
Note
Min
74
Max
Min
Max
Min
104
138
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
84
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
101
113
tRWC
tRAC
tCAC
tAA
45
12
23
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
3
3
tCLZ
tCEZ
tOLZ
tT
Output buffer turn-off delay from CAS
OE to output in Low-Z
13
50
13
50
13
50
6,13
3
3
3
3
Transition time (rise and fall)
RAS precharge time
1
1
1
2
25
45
8
30
50
8
40
60
10
40
10
14
12
5
tRP
RAS pulse width
10K
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
35
7
38
8
CAS pulse width
5K
33
22
10K
37
10K
45
14
4
RAS to CAS delay time
11
9
11
9
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
5
5
0
0
0
7
7
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
0
7
7
10
30
0
23
0
25
0
0
0
0
8
8
0
0
0
7
7
10
10
10
10
0
6
7
8
8
tRWL
tCWL
tDS
7
7
0
0
9