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K4E640812D-JP450 PDF预览

K4E640812D-JP450

更新时间: 2024-01-17 03:30:25
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
21页 194K
描述
DRAM

K4E640812D-JP450 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliant风险等级:5.75
Base Number Matches:1

K4E640812D-JP450 数据手册

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Industrial Temperature  
K4E660812D,K4E640812D  
CMOS DRAM  
8M x 8bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random  
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-  
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden  
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricated using  
Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.  
FEATURES  
• Extended Data Out Mode operation  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Self-refresh capability (L-ver only)  
• Fast parallel test mode capability  
• Part Identification  
- K4E660812D-JI/P(3.3V, 8K Ref.)  
- K4E640812D-JI/P(3.3V, 4K Ref.)  
- K4E660812D-TI/P(3.3V, 8K Ref.)  
- K4E640812D-TI/P(3.3V, 4K Ref.)  
• LVTTL(3.3V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
Active Power Dissipation  
Unit : mW  
Speed  
-45  
8K  
4K  
• Available in Plastic SOJ and TSOP(II) packages  
• +3.3V ±0.3V power supply  
324  
288  
252  
432  
396  
360  
-50  
Industrial Temperature operating ( -40~85°C)  
-60  
Refresh Cycles  
FUNCTIONAL BLOCK DIAGRAM  
Part  
NO.  
Refresh  
cycle  
Refresh time  
Normal  
L-ver  
RAS  
CAS  
W
Vcc  
Vss  
K4E660812D*  
K4E640812D  
8K  
4K  
Control  
Clocks  
64ms  
128ms  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)  
CAS -before-RAS & Hidden refresh mode  
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)  
Row Decoder  
Refresh Timer  
Data in  
Buffer  
Refresh Control  
Refresh Counter  
Memory Array  
8,388,608 x 8  
Cells  
DQ0  
to  
¡
Ü
Performance Range:  
DQ7  
Data out  
Buffer  
Row Address Buffer  
Col. Address Buffer  
A0~A12  
(A0~A11)*1  
Speed  
-45  
tRAC  
45ns  
50ns  
60ns  
tCAC  
12ns  
13ns  
15ns  
tRC  
tHPC  
17ns  
20ns  
25ns  
OE  
74ns  
84ns  
104ns  
A0~A9  
(A0~A10)*1  
Column Decoder  
-50  
Note) *1 : 4K Refresh  
-60  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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