Revisions — Intel® 82576 GbE Controller
Revision
Date
Comments
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Section 7.10.3.2.1, Filtering Capabilities - Typo corrected. In bullet, VM changed to
VF. Below:
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Promiscuous multicast & enable broadcast per VF.
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Section 7.10.3.8, Offloads - Note added; text below:
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NOTE: VLAN strip offload is determined based only on the L2 MAC address. In
order to make sure VLAN strip offload is correctly applied, all packets should be
initially forwarded using one of the L2 MAC address filters (RAH/RAL, UTA,
MTA, VMOLR.BAM, VMOLR.MPE.
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Two table titles corrected. Could have caused confusion. Minor edits also made to
field descriptions.
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Table 7-35, TCP/IP or UDP/IP Packet Format Sent by Host
Table 7-36, TCP/IP or UDP/IP Packet Format Sent by 82576
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Section 8.10.7, Receive Descriptor Ring Length - RDLEN (0x0C008 + 0x40*n
[n=0...15]; R/W) - Description updated. LEN text added: The maximum allowed
value is 0x80000 (32K descriptors).
Section 8.12.2, Transmit Control Extended - TCTL_EXT (0x0404; R/W) - Default
value of COLD corrected (0x42) in text description.
Section 10.5.10.1.4, Force TCO Command - Clarification note added to table. See
below:
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NOTE: Before initiating a Firmware reset command, one should disable TCO
receive via Receive Enable Command -- setting RCV_EN to 0 -- and wait for 200
milliseconds before initiating Firmware Reset command. In addition, the
MCshould not transmit during this period.
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Section 10.5.10.2.1, Receive TCO LAN Packet Transaction - Receive TCO packet
format table updated; numerous changes. For clarity.
Section 10.7.10, Read Fail-Over Configuration Host Command - Both tables in
section updated.
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Table 10-49, Commands to Read the Fail-Over Configuration Register - Last row
in table deleted; was incorrect.
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Table 10-50, States Returned - Description column (byte 1) updated.
Description was confusing.
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Section 10.5.12.3.1, Example 3 - Pseudo Code - Pseudo Code, step 5: MAC Address
Filtering is bit 0, not bit 1. Also the MDEF value is 00000009 and not 00000040.
Section 10.5.12.4.1, Example 4 - Pseudo Code - Step 5: Configure MDEF[0], MDEF
value is 0000004 and not 00000040.
2.44
10/14/2009
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Section 9.6.4.3, PCIe SR-IOV Control Register (0x168; RW); Bit 4; ARI Capable
Hierarchy. Text updated.
Section 10.0, System Manageability; More information on MACSec parameters
provided. See Section 10.5.10.1.6, Update MACSec Parameters and Section 10.8,
MACSec and Manageability in particular.
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Section 10.5.10.1.3, Receive Enable Command; Section 10.5.10.2.5, Read
Management Receive Filter Parameters. Bit order expression corrected in two
tables. See bold text.
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References to BMC changed to MC if the reference is not programmatic.
Section 3.3.1.6, EEPROM Recovery. Section now exposed in the datasheet.
2.45
10/30/2009
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Section 8.10.8, Receive Descriptor Head - RDH (0x0C010 + 0x40*n [n=0...15];
RO) and Section 8.12.11, Transmit Descriptor Head - TDH (0x0E010 + 0x40*n
[n=0...15]; RO). Both registers indicated RW incorrectly. Changed to RO.
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Table 10-33, Supported NC-SI Commands and Table 10-34, Optional NC-SI
Features Support. List of supported commands/functions updated to correct an
error in our support statements. See bold text in both tables.
320961-015EN
Revision: 2.61
December 2010
Intel® 82576 GbE Controller
Datasheet
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