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JL82576NSSLBAD PDF预览

JL82576NSSLBAD

更新时间: 2024-01-15 02:47:03
品牌 Logo 应用领域
英特尔 - INTEL 通信时钟局域网外围集成电路
页数 文件大小 规格书
934页 7188K
描述
LAN Controller, CMOS, PBGA576, 25 X 25 MM, 1 MM PITCH, BGA-576

JL82576NSSLBAD 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:576
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.75地址总线宽度:
边界扫描:NO最大时钟频率:25 MHz
通信协议:ASYNC, BIT; I2C外部数据总线宽度:
JESD-30 代码:S-PBGA-B576长度:25 mm
低功率模式:YES端子数量:576
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:25 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

JL82576NSSLBAD 数据手册

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Revisions — Intel® 82576 GbE Controller  
Revision  
Date  
Comments  
Section 7.10.3.2.1, Filtering Capabilities - Typo corrected. In bullet, VM changed to  
VF. Below:  
Promiscuous multicast & enable broadcast per VF.  
Section 7.10.3.8, Offloads - Note added; text below:  
NOTE: VLAN strip offload is determined based only on the L2 MAC address. In  
order to make sure VLAN strip offload is correctly applied, all packets should be  
initially forwarded using one of the L2 MAC address filters (RAH/RAL, UTA,  
MTA, VMOLR.BAM, VMOLR.MPE.  
Two table titles corrected. Could have caused confusion. Minor edits also made to  
field descriptions.  
Table 7-35, TCP/IP or UDP/IP Packet Format Sent by Host  
Table 7-36, TCP/IP or UDP/IP Packet Format Sent by 82576  
Section 8.10.7, Receive Descriptor Ring Length - RDLEN (0x0C008 + 0x40*n  
[n=0...15]; R/W) - Description updated. LEN text added: The maximum allowed  
value is 0x80000 (32K descriptors).  
Section 8.12.2, Transmit Control Extended - TCTL_EXT (0x0404; R/W) - Default  
value of COLD corrected (0x42) in text description.  
Section 10.5.10.1.4, Force TCO Command - Clarification note added to table. See  
below:  
NOTE: Before initiating a Firmware reset command, one should disable TCO  
receive via Receive Enable Command -- setting RCV_EN to 0 -- and wait for 200  
milliseconds before initiating Firmware Reset command. In addition, the  
MCshould not transmit during this period.  
Section 10.5.10.2.1, Receive TCO LAN Packet Transaction - Receive TCO packet  
format table updated; numerous changes. For clarity.  
Section 10.7.10, Read Fail-Over Configuration Host Command - Both tables in  
section updated.  
Table 10-49, Commands to Read the Fail-Over Configuration Register - Last row  
in table deleted; was incorrect.  
Table 10-50, States Returned - Description column (byte 1) updated.  
Description was confusing.  
Section 10.5.12.3.1, Example 3 - Pseudo Code - Pseudo Code, step 5: MAC Address  
Filtering is bit 0, not bit 1. Also the MDEF value is 00000009 and not 00000040.  
Section 10.5.12.4.1, Example 4 - Pseudo Code - Step 5: Configure MDEF[0], MDEF  
value is 0000004 and not 00000040.  
2.44  
10/14/2009  
Section 9.6.4.3, PCIe SR-IOV Control Register (0x168; RW); Bit 4; ARI Capable  
Hierarchy. Text updated.  
Section 10.0, System Manageability; More information on MACSec parameters  
provided. See Section 10.5.10.1.6, Update MACSec Parameters and Section 10.8,  
MACSec and Manageability in particular.  
Section 10.5.10.1.3, Receive Enable Command; Section 10.5.10.2.5, Read  
Management Receive Filter Parameters. Bit order expression corrected in two  
tables. See bold text.  
References to BMC changed to MC if the reference is not programmatic.  
Section 3.3.1.6, EEPROM Recovery. Section now exposed in the datasheet.  
2.45  
10/30/2009  
Section 8.10.8, Receive Descriptor Head - RDH (0x0C010 + 0x40*n [n=0...15];  
RO) and Section 8.12.11, Transmit Descriptor Head - TDH (0x0E010 + 0x40*n  
[n=0...15]; RO). Both registers indicated RW incorrectly. Changed to RO.  
Table 10-33, Supported NC-SI Commands and Table 10-34, Optional NC-SI  
Features Support. List of supported commands/functions updated to correct an  
error in our support statements. See bold text in both tables.  
320961-015EN  
Revision: 2.61  
December 2010  
Intel® 82576 GbE Controller  
Datasheet  
5

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