Intel® 82576 GbE Controller — Contents
3.1.6.1
3.1.6.2
3.1.6.3
3.1.6.4
3.1.6.5
3.1.6.6
3.1.6.7
Link Width ................................................................................................................... 90
Polarity Inversion.......................................................................................................... 90
L0s Exit latency ............................................................................................................ 91
Lane-to-Lane De-Skew .................................................................................................. 91
Lane Reversal............................................................................................................... 91
Reset .......................................................................................................................... 92
Scrambler Disable......................................................................................................... 92
Error Events and Error Reporting........................................................................................... 92
Mechanism in General.................................................................................................... 92
Error Events................................................................................................................. 93
Error Pollution .............................................................................................................. 95
Completion with Unsuccessful Completion Status............................................................... 95
Error Reporting Changes................................................................................................ 95
Performance Monitoring ....................................................................................................... 96
Leaky Bucket Mode ....................................................................................................... 96
PCIe Power Management...................................................................................................... 97
PCIe Programming Interface................................................................................................. 97
Management Interfaces.............................................................................................................. 97
SMBus ............................................................................................................................... 97
3.1.7
3.1.7.1
3.1.7.2
3.1.7.3
3.1.7.4
3.1.7.5
3.1.8
3.1.8.1
3.1.9
3.1.10
3.2
3.2.1
3.2.1.1
3.2.1.1.1
3.2.1.1.2
Channel Behavior.......................................................................................................... 97
SMBus Addressing...................................................................................................... 97
SMBus Notification Methods......................................................................................... 98
3.2.1.1.2.1
3.2.1.1.2.2
3.2.1.1.2.3
3.2.1.1.3
3.2.1.1.4
3.2.1.1.5
3.2.1.1.6
3.2.1.1.7
3.2.1.1.8
3.2.1.1.8.1
3.2.1.1.8.2
3.2.1.1.8.3
3.2.1.1.9
SMBus Alert and Alert Response Method ................................................................. 98
Asynchronous Notify Method ................................................................................. 99
Direct Receive Method.......................................................................................... 99
Receive TCO Flow .....................................................................................................100
Transmit TCO Flow....................................................................................................100
Transmit Errors in Sequence Handling..........................................................................101
TCO Command Aborted Flow ......................................................................................102
Concurrent SMBus Transactions ..................................................................................102
SMBus ARP Functionality............................................................................................102
SMBus ARP in Dual-/Single-Address Mode..............................................................102
SMBus ARP Flow.................................................................................................103
SMBus ARP UDID Content................................................................................104
LAN Fail-Over Through SMBus ....................................................................................106
3.2.2
3.2.2.1
3.2.2.2
NC-SI .............................................................................................................................. 106
Electrical Characteristics ...............................................................................................106
NC-SI Transactions ......................................................................................................107
3.3
3.3.1
3.3.1.1
3.3.1.2
Flash / EEPROM....................................................................................................................... 107
EEPROM Interface ............................................................................................................. 107
General Overview.........................................................................................................107
EEPROM Device ...........................................................................................................108
Software Accesses .......................................................................................................108
Signature Field ............................................................................................................108
Protected EEPROM Space ..............................................................................................109
Initial EEPROM Programming ......................................................................................109
Activating the Protection Mechanism............................................................................109
Non Permitted Accessing to Protected Areas in the EEPROM............................................109
EEPROM Recovery........................................................................................................110
EEPROM-Less Support ..................................................................................................110
Access to the EEPROM Controlled Feature.....................................................................111
3.3.1.3
3.3.1.4
3.3.1.5
3.3.1.5.1
3.3.1.5.2
3.3.1.5.3
3.3.1.6
3.3.1.7
3.3.1.7.1
3.3.2
3.3.2.1
3.3.2.2
3.3.3
3.3.4
3.3.4.1
3.3.4.2
3.3.4.3
Shared EEPROM ................................................................................................................ 112
EEPROM Deadlock Avoidance.........................................................................................112
EEPROM Map Shared Words ..........................................................................................112
Vital Product Data (VPD) Support ........................................................................................ 113
Flash Interface.................................................................................................................. 114
Flash Interface Operation..............................................................................................114
Flash Write Control.......................................................................................................115
Flash Erase Control ......................................................................................................115
Shared FLASH................................................................................................................... 115
Flash Access Contention................................................................................................115
3.3.5
3.3.5.1
Intel® 82576 GbE Controller
Datasheet
10
320961-015EN
Revision: 2.61
December 2010
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