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IW4019BDW PDF预览

IW4019BDW

更新时间: 2024-01-25 01:52:33
品牌 Logo 应用领域
其他 - ETC
页数 文件大小 规格书
5页 278K
描述
Quad AND/OR Select Gate

IW4019BDW 数据手册

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TECHNICAL DATA  
IW4019B  
Quad AND/OR Select Gate  
High-Voltage Silicon-Gate CMOS  
The IW4019B types consist of four AND/OR select gate  
configurations, each consisting of two 2-input AND gates driving a single  
2-input gate. Selection is accomplished by control bits Sa and Sb .In  
addition to selection of either channel A or channel B information, the  
control bits can be applied simultaneously to accomplish the logical A + B  
function  
Operating Voltage Range: 3.0 to 18 V  
Maximum input current of 1 µA at 18 V over full package-temperature  
range; 100 nA at 18 V and 25°C  
Noise margin (over full package temperature range):  
ORDERING INFORMATION  
IW4019BN Plastic  
IW4019BDW SOIC  
TA = -55° to 125° C for all packages  
1.0 V min @ 5.0 V supply  
2.0 V min @ 10.0 V supply  
2.5 V min @ 15.0 V supply  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
FUNCTION TABLE  
Inputs  
Sb  
Outputs  
Sa  
H
H
L
A
H
L
B
X
X
H
L
Y
H
L
L
L
H
H
L
X
X
X
L
H
L
L
L
X
L
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
PIN 16 =VCC  
PIN 8 = GND  
H
1

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