Datasheet > IW4023BN

IW4023BN

更新时间： 2024-01-28 16:23:15

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IW4023BN 数据手册

TECHNICAL DATA

IW4023B

Triple 3-Input NAND Gate

High-Voltage Silicon-Gate CMOS

The IW4023B NAND gates provide the system designer with direct

emplementation of the NAND function.

•

Operating Voltage Range: 3.0 to 18 V

Maximum input current of 1 μA at 18 V over full package-temperature

range; 100 nA at 18 V and 25°C

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

ORDERING INFORMATION

IW4023BN Plastic

IW4023BD SOIC

T_A= -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Output

PIN 14 =V_CC

PIN 7 = GND

X = don’t care

Rev. 00

12 3 4 5

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