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IW4021B PDF预览

IW4021B

更新时间: 2024-01-02 00:44:22
品牌 Logo 应用领域
IKSEMICON 移位寄存器高压
页数 文件大小 规格书
5页 187K
描述
8-Bit Shift Register High-Voltage Silicon-Gate CMOS

IW4021B 数据手册

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TECHNICAL DATA  
IW4021B  
8-Bit Shift Register  
High-Voltage Silicon-Gate CMOS  
The IW4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-to-  
Serial Converter) with a synchronous Serial Data Input (DS), a Clock  
Input (CP), an asynchronous active HIGH Parallel Load Input (PL), eight  
asynchronous Parallel Data Inputs (P0-P7) and Buffered Parallel Outputs  
from the last three stages (Q5-Q7).  
Information on the Parallel Data Inputs (P0-P7) is asynchronously  
loaded into the register while the Parallel Load Input (PL) is HIGH,  
independent of the Clock (CP) and Serial Data (DS) inputs. Data present  
in the register is stored on the HIGH-to-LOW transition of the Parallel  
Load Input (PL).  
When the Parallel Load Input is LOW, data on the Serial Data Input  
(DS) is shifted into the first register position and all the data in the register  
is shifted one position to the right on the LOW-to-HIGH transition of the  
Clock Input (CP).  
ORDERING INFORMATION  
IW4021BN Plastic  
IW4021BDW SOIC  
TA = -55° to 125° C for all packages  
Operating Voltage Range: 3.0 to 18 V  
Maximum input current of 1 μA at 18 V over full package-temperature  
range; 100 nA at 18 V and 25°C  
PIN ASSIGNMENT  
Noise margin (over full package temperature range):  
1.0 V min @ 5.0 V supply  
2.0 V min @ 10.0 V supply  
2.5 V min @ 15.0 V supply  
LOGIC DIAGRAM  
FUNCTION TABLE  
SERIAL OPERATION:  
Q5  
Q6  
Q7  
t
CP  
DS  
PL  
t=n+6 t=n+7 t=n+8  
n
0
1
0
0
0
0
0
0
n+1  
n+2  
n+3  
1
0
0
1
0
0
1
1
1
0
X
Q5  
Q6  
Q7  
PARALLEL OPERATION:  
CP  
X
DS  
X
PL P5 P6 P7 Q5 Q6 Q7  
1
D
D
D
D
D
D
X = don’t care  
D = 1 or 0  
PIN 16 =VCC  
PIN 8 = GND  
Rev. 00  

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