Datasheet > IT6605E

IT6605E

更新时间： 2022-08-07 18:38:14

品牌	Logo	应用领域
ITE		/
页数	文件大小	规格书
38页	775K
描述
Single-Link HDMI Transmitter

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IT6605E 数据手册

IT6605

connected port.

Figure 3. Video data processing flow of the IT6605

Video Data Processing Flow

Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most

of the block enablings and path bypassings are controlled through register programming. Please refer

to IT6605 Programming Guide for detailed and precise descriptions.

As can be seen from Figure 3, the received and recovered HDMI raw data is first HDCP-decrypted.

The extracted video data then go through various processing blocks, as described in the following

paragraphs, before outputting the proper video format to the backend video controller.

The video processing including YCbCr up/down-sampling, color-space conversion and dithering.

Depending on the selected input and output video formats, different processing blocks are either

enabled or bypassed via register control. For the sake of flexibility, this is all done in software register

programming. Therefore, extra care should be taken in keeping the selected output format and the

corresponding video processing block selection. Please refer to the IT6605 Programming Guide for

suggested register setting.

Designated as QE[35:0], the output video data could take on bus width of 8 bits to 36 bits, depending

on the formats and color depths. The output interface could be configured through register setting to

provide various data formats as listed in Table 1 in order to cater to different preferences of different

backend controllers.

Feb-2012 Rev:0.92 9/38

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