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ISL9305IRTBCNLZ-T PDF预览

ISL9305IRTBCNLZ-T

更新时间: 2024-02-03 00:20:30
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
17页 1036K
描述
3MHz Dual Step-Down Converters and Dual Low-Input LDOs with I<sup>2</sup>C Compatible Interface; TQFN16; Temp Range: -40&deg; to 85&deg;C

ISL9305IRTBCNLZ-T 技术参数

生命周期:Unknown零件包装代码:TQFN
包装说明:HVQCCN, LCC16,.16SQ,25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:17 weeks
风险等级:5.66Is Samacsys:N
可调阈值:YES模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码:S-PQCC-N16JESD-609代码:e3
长度:4 mm湿度敏感等级:3
信道数量:1功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC16,.16SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5/5 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Power Management Circuits最大供电电流 (Isup):7.5 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

ISL9305IRTBCNLZ-T 数据手册

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ISL9305  
Package Outline Drawing  
L16.4x4G  
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE  
Rev 0, 4/10  
4X  
1.95  
4.00  
0.65  
12X  
A
6
B
13  
16  
PIN #1  
INDEX AREA  
6
PIN 1  
INDEX AREA  
1
12  
2 . 10 ± 0 . 10  
9
4
(4X)  
0.15  
8
5
0.10 M C A B  
0.30 ± 0.05  
16X 0 . 50 ± 0 . 1  
TOP VIEW  
4
BOTTOM VIEW  
SEE DETAIL "X"  
C
0.10  
C
0.75  
BASE PLANE  
SEATING PLANE  
0.08 C  
SIDE VIEW  
( 3 . 6 TYP )  
(
( 12X 0 . 65 )  
2 . 10 )  
5
0 . 2 REF  
C
( 16X 0 . 30 )  
( 16 X 0 . 70 )  
0 . 00 MIN.  
0 . 05 MAX.  
TYPICAL RECOMMENDED LAND PATTERN  
DETAIL "X"  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.  
3.  
Unless otherwise specified, tolerance : Decimal ± 0.05  
4. Dimension applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
JEDEC reference drawing: MO220K.  
7.  
FN7605 Rev 2.00  
February 9, 2015  
Page 17 of 17  

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