ISL9000AIRFJZ PDF预览

ISL9000AIRFJZ

更新时间: 2025-07-19 18:17:03
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
14页 718K
描述
Dual LDO with Low Noise, Very High PSRR, and Low IQ

ISL9000AIRFJZ 技术参数

生命周期:Unknown零件包装代码:DFN
包装说明:HVSON, SOLCC10,.11,20针数:10
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:19 weeks
风险等级:5.17可调性:FIXED
最大回动电压 1:0.4 V标称回动电压 1:0.25 V
最大回动电压 2:0.4 V最大绝对输入电压:7.1 V
最大输入电压:6.5 V最小输入电压:2.3 V
JESD-30 代码:S-PDSO-N10JESD-609代码:e3
长度:3 mm湿度敏感等级:1
功能数量:1输出次数:2
端子数量:10工作温度TJ-Max:125 °C
工作温度TJ-Min:-40 °C最大输出电流 1:0.3 A
最大输出电流 2:0.3 A最大输出电压 1:2.545 V
最小输出电压 1:2.455 V标称输出电压 1:2.5 V
最大输出电压 2:2.8504 V最小输出电压 2:2.7496 V
标称输出电压 2:2.8 V封装主体材料:PLASTIC/EPOXY
封装代码:HVSON封装等效代码:SOLCC10,.11,20
封装形状:SQUARE封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
调节器类型:FIXED POSITIVE MULTIPLE OUTPUT LDO REGULATOR座面最大高度:1 mm
子类别:Other Regulators表面贴装:YES
技术:CMOS端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
最大电压容差:1.8%宽度:3 mm
Base Number Matches:1

ISL9000AIRFJZ 数据手册

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DATASHEET  
ISL9000A  
FN6391  
Rev 3.00  
October 15, 2015  
Dual LDO with Low Noise, Very High PSRR and Low IQ  
ISL9000A is a high performance dual LDO capable of sourcing  
300mA current from each output. It has a low standby current  
and very high PSRR and is stable with output capacitance of  
1µF to 10µF with ESR of up to 200m.  
Features  
• Integrates two 300mA high performance LDOs  
• Excellent transient response to large current steps  
• ±1.8% accuracy over all operating conditions  
The device integrates an individual Power-On-Reset (POR)  
function for each output. The POR delay for VO2 can be  
externally programmed by connecting a timing capacitor to the  
CPOR pin. The POR delay for VO1 is internally fixed at  
approximately 2ms. A reference bypass pin is also provided for  
connecting a noise filtering capacitor for low noise and high-  
PSRR applications.  
• Excellent load regulation: < 0.1% voltage change across full  
range of load current  
• Low output noise: typically 30µV  
• Very high PSRR: 90dB @ 1kHz  
@ 100µA (1.5V)  
RMS  
• Extremely low quiescent current: 42µA (both LDOs active)  
• Wide input voltage capability: 2.3V to 6.5V  
The quiescent current is typically only 42µA with both LDO’s  
enabled and active. Separate enable pins control each  
individual LDO output. When both enable pins are low, the  
device is in shutdown, typically drawing less than 0.1µA.  
• Low dropout voltage: typically 200mV @ 300mA  
• Stable with 1µF to 10µF ceramic capacitors  
• Separate enable and POR pins for each LDO  
Several combinations of voltage outputs are standard. Output  
voltage options for each LDO range from 1.5V to 3.3V. Other  
output voltage options may be available upon request.  
• Soft-start and staged turn-on to limit input current surge  
during enable  
• Current limit and overheat protection  
• Tiny 10 Ld 3mmx3mm DFN package  
• -40°C to +85°C operating temperature range  
• Pb-free (RoHS compliant)  
Applications  
• PDAs, Cell Phones and Smart Phones  
• Portable Instruments, MP3 Players  
• Handheld Devices including Medical Handheld  
ISL9000A  
10  
1
VIN (2.3 TO 6.5V)  
VO1  
VIN  
VO1  
VO2  
ON  
ON  
9
2
EN1  
VO2  
ENABLE1  
ENABLE2  
VO2 OK  
VO2 TOO LOW  
OK  
OFF  
OFF  
8
3
4
EN2  
POR2  
POR1  
RESET2  
(200ms DELAY,  
C3 = 0.01µF)  
7
6
CBYP  
V
OUT1  
5
CPOR  
GND  
RESET1  
(2ms DELAY)  
VO1 TOO LOW  
C1  
C2  
C3  
C4  
C5  
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR  
C2: 0.1µF X7R CERAMIC CAPACITOR  
C3: 0.01µF X7R CERAMIC CAPACITOR  
FIGURE 1. TYPICAL APPLICATION  
FN6391 Rev 3.00  
October 15, 2015  
Page 1 of 14  

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