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ISL8016IR12Z PDF预览

ISL8016IR12Z

更新时间： 2024-02-02 04:42:48
品牌 Logo 应用领域
英特矽尔 - INTERSIL 稳压器开关
页数 文件大小 规格书
22页 1132K
描述
6A Low Quiescent Current High Efficiency Synchronous Buck Regulator

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ISL8016IR12Z 技术参数

生命周期：Unknown零件包装代码：QFN
包装说明：HVQCCN, LCC20,.12X.16,20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：17 weeks
风险等级：5.14其他特性：ALSO HAS A CONTROL TECHNIQUE OF PFM
模拟集成电路 - 其他类型：SWITCHING REGULATOR控制模式：CURRENT-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：5.5 V
最小输入电压：2.7 V标称输入电压：3.6 V
JESD-30 代码：R-PQCC-N20JESD-609代码：e3
长度：4 mm湿度敏感等级：3
功能数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
最大输出电流：11.5 A标称输出电压：1.2 V
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC20,.12X.16,20封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：BUCK最大切换频率：4500 kHz
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：3 mmBase Number Matches：1

ISL8016IR12Z 数据手册

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ISL8016  
Pin Descriptions  
PIN  
1, 19, 20  
2, 3, 4  
5, 6, 7  
8
SYMBOL  
PGND  
PHASE  
VIN  
DESCRIPTION  
Power ground.  
Switching node connection. Connect to one terminal of the inductor.  
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.  
PG  
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connected between VIN and  
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.  
9
SYNCOUT  
SYNCIN  
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or  
SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V.  
SYNCOUT is held at 0V in PFM light load to reduce quiescent current.  
10  
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or  
ground for PFM mode. Connect to an external function generator for synchronization with the positive  
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state if SYNCIN  
is floating.  
11  
12  
EN  
FS  
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the  
output capacitor when driven to low. There is an internal 1MΩ pull-down resistor to prevent an  
undefined logic state in case of EN pin float.  
This pin sets the oscillator switching frequency, using a resistor, R , from the FS pin to GND. The  
FS  
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz  
and configured for internal compensation if FS is connected to VIN.  
13  
14  
VSET  
ISET  
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for  
no margining, and connect to VIN for +10%.  
ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND  
for 2A, to VIN for 4A, and keep it floating for 6A.  
15  
SS  
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor  
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.  
16, 17  
COMP, VFB  
The feedback network of the regulator, VFB, is the negative input to the transconductance error  
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used  
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider  
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage  
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical  
applications, an external compensation network may offer improved performance for some designs.  
In addition to regulation, VFB is also used to determine the state of PG.  
Short VFB to OUTPUT when using one of the available fixed VOUT options.  
18  
SGND  
EPAD  
Signal ground.  
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many  
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.  
FN7616.1  
May 5, 2011  
3
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