ISL78840ASxH, ISL78841ASxH, ISL78843ASxH, ISL78845ASxH, ISL738840ASEH, ISL738841ASEH, ISL738843ASEH, ISL738845ASEH
Pin Configurations
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH,
ISL78840ASRH, ISL78841ASRH, ISL78843ASRH, ISL78845ASRH,
ISL738840ASEH, ISL738841ASEH, ISL738843ASEH, ISL738845ASEH
(8 LD FLATPACK)
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH,
ISL78845ASEH, ISL78840ASRH, ISL78841ASRH,
ISL78843ASRH, ISL78845ASRH
(8 LD SBDIP)
TOP VIEW
TOP VIEW
COMP
FB
1
2
3
4
8
7
6
5
V
V
REF
COMP
FB
1
2
3
4
8
7
6
5
V
V
REF
DD
DD
CS
OUT
GND
CS
OUT
GND
RTCT
RTCT
Pin Descriptions
PIN NAME
PIN NUMBER
ESD CIRCUIT
DESCRIPTION
The oscillator timing control pin. The operational frequency and maximum duty cycle are set by
RTCT
4
1
connecting a resistor, RT, between V
and this pin and a timing capacitor, CT, from this pin to GND.
REF
The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The
charge time, t , the discharge time, t , the RTCT oscillator frequency, f, and the maximum duty cycle,
C
D
D
, can be approximated from Equations 1 through 4:
MAX
t
0.533 RT CT
(EQ. 1)
(EQ. 2)
C
0.008 RT – 3.83
---------------------------------------------
t
–RT CT In
D
0.008 RT – 1.71
f = 1 t + t
(EQ. 3)
(EQ. 4)
C
D
D = t f
C
The formulas have increased error at higher frequencies due to propagation delays. Figure 7 may be
used as a guideline in selecting the capacitor and resistor values required for a given oscillator
frequency for the ISL7884xASxH and ISL73884xASEH . The switching frequency for the
ISL78841ASxH/ISL738841ASEH and ISL78845ASxH/ISL738845ASEH will be half the RTCT oscillator
frequency.
COMP
1
2
3
1
1
1
COMP is the output of the error amplifier and the input of the PWM comparator. The control loop
frequency compensation network is connected between the COMP and FB pins.
FB
CS
The output voltage feedback is connected to the inverting input of the error amplifier through this pin.
The noninverting input of the error amplifier is internally tied to a reference voltage.
The current sense input to the PWM comparator. The range of the input signal is nominally 0V to 1.0V
and has an internal offset of 100mV.
GND
OUT
5
6
-
GND is the power and small signal reference ground for all functions.
3
The drive output to the power switching device. It is a high current output capable of driving the gate of
a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VDD is below
the UVLO threshold.
V
7
2
V
is the power connection for the device. The total supply current will depend on the load applied to
DD
DD
OUT. Total I current is the sum of the operating current and the average output current. Knowing the
DD
operating frequency, f and the MOSFET gate charge, Qg, the average output current can be calculated
from Equation 5:
I
= Qg f
(EQ. 5)
OUT
To optimize noise immunity, bypass V to GND with a ceramic capacitor as close to the V and GND
DD
DD
pins as possible.
FN7952 Rev.4.00
Feb 25, 2020
Page 4 of 18
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