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ISL6520AIRZ PDF预览

ISL6520AIRZ

更新时间： 2024-01-24 10:42:09
品牌 Logo 应用领域
瑞萨 - RENESAS 开关
页数 文件大小 规格书
12页 662K
描述
SWITCHING CONTROLLER, 340kHz SWITCHING FREQ-MAX, PQCC16, 4 X 4 MM, LEAD FREE, PLASTIC, MO-220-VGGC, QFN-16

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ISL6520AIRZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC16,.16SQ,25针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.55
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：VOLTAGE-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：5.5 V
最小输入电压：4.5 V标称输入电压：5 V
JESD-30 代码：S-PQCC-N16JESD-609代码：e3
长度：4 mm湿度敏感等级：3
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC16,.16SQ,25封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：PUSH-PULL最大切换频率：340 kHz
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：4 mmBase Number Matches：1

ISL6520AIRZ 数据手册

 浏览型号ISL6520AIRZ的Datasheet PDF文件第4页浏览型号ISL6520AIRZ的Datasheet PDF文件第5页浏览型号ISL6520AIRZ的Datasheet PDF文件第6页浏览型号ISL6520AIRZ的Datasheet PDF文件第8页浏览型号ISL6520AIRZ的Datasheet PDF文件第9页浏览型号ISL6520AIRZ的Datasheet PDF文件第10页 
ISL6520A  
pulse-width modulated (PWM) wave with an amplitude of  
at the PHASE node. The PWM wave is smoothed by the  
V
IN  
V
IN  
output filter (L and C ).  
ISL6520A  
O
O
V
IN  
DRIVER  
DRIVER  
UGATE  
Q
Q
OSC  
1
L
O
PWM  
V
OUT  
PHASE  
L
O
COMPARATOR  
V
OUT  
-
PHASE  
C
IN  
2
+
V  
C
O
OSC  
LGATE  
C
O
ESR  
(PARASITIC)  
Z
FB  
RETURN  
V
E/A  
Z
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND  
GROUND PLANES OR ISLANDS  
-
IN  
+
REFERENCE  
ERROR  
AMP  
Figure 3 shows the critical power components of the converter.  
To minimize the voltage overshoot, the interconnecting wires  
indicated by heavy lines should be part of a ground or power  
plane in a printed circuit board. The components shown in  
Figure 3 should be located as close together as possible.  
Please note that the capacitors C and C may each  
DETAILED COMPENSATION COMPONENTS  
Z
FB  
V
OUT  
C
2
Z
IN  
C
C
R
R
3
1
3
2
IN  
O
represent numerous physical capacitors. Locate the ISL6520A  
within 3 inches of the MOSFETs, Q and Q . The circuit traces  
R
1
1
2
COMP  
for the MOSFETs’ gate and source connections from the  
ISL6520A must be sized to handle up to 1A peak current.  
FB  
-
+
Figure 4 shows the circuit traces that require additional  
layout consideration. Use single point and ground plane  
construction for the circuits shown. Minimize any leakage  
current paths on the COMP/OCSET pin and locate the  
ISL6520A  
REFERENCE  
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER  
COMPENSATION DESIGN  
resistor, R  
close to the COMP/OCSET pin because  
OSCET  
The modulator transfer function is the small-signal transfer  
function of V /V . This function is dominated by a DC  
the internal current source is only 20µA. Provide local V  
decoupling between VCC and GND pins. Locate the  
CC  
OUT E/A  
Gain and the output filter (L and C ), with a double pole  
capacitor, C  
as close as practical to the BOOT and  
O
O
BOOT  
break frequency at F and a zero at F  
the modulator is simply the input voltage (V ) divided by the  
peak-to-peak oscillator voltage V  
OSC  
. The DC Gain of  
PHASE pins. All components used for feedback  
compensation should be located as close to the IC a  
practical.  
LC ESR  
IN  
.
+V  
IN  
BOOT  
Modulator Break Frequency Equations  
D
1
Q
1
+5V  
L
O
C
BOOT  
1
1
V
F
= ------------------------------------------  
F
= -------------------------------------------  
OUT  
LC  
ESR  
2x ESR x C  
2x  
L
x C  
O
PHASE  
VCC  
O
O
ISL6520A  
(EQ. 4)  
C
O
+5V  
Q
2
The compensation network consists of the error amplifier  
(internal to the ISL6520A) and the impedance networks Z  
COMP/OCSET  
GND  
IN  
C
VCC  
and Z . The goal of the compensation network is to provide  
FB  
a closed loop transfer function with the highest 0dB crossing  
frequency (f  
) and adequate phase margin. Phase margin  
0dB  
is the difference between the closed loop phase at f  
180 degrees. The following equations relate the  
and  
0dB  
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL  
LAYOUT GUIDELINES  
compensation network’s poles, zeros and gain to the  
components (R , R , R , C , C , and C ) in Figure 7. Use  
1
2
3
1
2
3
Feedback Compensation  
these guidelines for locating the poles and zeros of the  
Figure 5 highlights the voltage-mode control loop for a  
compensation network:  
synchronous-rectified buck converter. The output voltage  
(V ) is regulated to the Reference voltage level. The  
1. Pick Gain (R /R ) for desired converter bandwidth.  
2
1
OUT  
ST  
2. Place 1 Zero Below Filter’s Double Pole (~75% F ).  
LC  
error amplifier (Error Amp) output (V ) is compared with  
E/A  
ND  
3. Place 2  
Zero at Filter’s Double Pole.  
the oscillator (OSC) triangular wave to provide a  
FN9016 Rev 6.00  
Dec 10, 2009  
Page 7 of 12  
 
 
 
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