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ISL6271ACR PDF预览

ISL6271ACR

更新时间: 2024-02-20 15:49:09
品牌 Logo 应用领域
英特矽尔 - INTERSIL 稳压器
页数 文件大小 规格书
16页 583K
描述
Integrated XScale Regulator

ISL6271ACR 技术参数

生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:20
Reach Compliance Code:unknown风险等级:5.73
模拟集成电路 - 其他类型:SWITCHING REGULATOR控制技术:PULSE WIDTH MODULATION
最大输入电压:5.5 V最小输入电压:2.76 V
标称输入电压:3.7 VJESD-30 代码:S-PQCC-N20
长度:4 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-25 °C最大输出电流:0.8 A
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度:1 mm表面贴装:YES
切换器配置:BUCK温度等级:OTHER
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:4 mm

ISL6271ACR 数据手册

 浏览型号ISL6271ACR的Datasheet PDF文件第10页浏览型号ISL6271ACR的Datasheet PDF文件第11页浏览型号ISL6271ACR的Datasheet PDF文件第12页浏览型号ISL6271ACR的Datasheet PDF文件第13页浏览型号ISL6271ACR的Datasheet PDF文件第14页浏览型号ISL6271ACR的Datasheet PDF文件第15页 
ISL6271A  
Quad Flat No-Lead Plas tic Package (QFN)  
Micro Lead Frame Plas tic Package (MLFP)  
L20.4x4  
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE  
(COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C)  
MILLIMETERS  
SYMBOL  
MIN  
NOMINAL  
MAX  
1.00  
0.05  
1.00  
NOTES  
A
A1  
A2  
A3  
b
0.80  
0.90  
-
-
-
-
-
-
9
0.20 REF  
9
0.18  
1.95  
1.95  
0.23  
0.30  
2.25  
2.25  
5, 8  
D
4.00 BSC  
-
D1  
D2  
E
3.75 BSC  
9
2.10  
7, 8  
4.00 BSC  
-
E1  
E2  
e
3.75 BSC  
9
2.10  
7, 8  
0.50 BSC  
-
k
0.25  
0.35  
-
-
-
-
L
0.60  
0.75  
0.15  
8
L1  
N
-
20  
5
5
-
10  
2
Nd  
Ne  
P
3
5
-
3
0.60  
12  
9
θ
-
-
9
Rev. 1 10/02  
NOTES:  
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.  
2. N is the number of terminals.  
3. Nd and Ne refer to the number of terminals on each D and E.  
4. All dimensions are in millimeters. Angles are in degrees.  
5. Dimension b applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
6. The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
7. Dimensions D2 and E2 are for the exposed pads which provide  
improved electrical and thermal performance.  
8. Nominal dimensionsare provided toassistwith PCBLandPattern  
Design efforts, see Intersil Technical Brief TB389.  
9. Features and dimensions A2, A3, D1, E1, P & θ are present when  
Anvil singulation method is used and not present for saw  
singulation.  
10. Depending on the method of lead termination at the edge of the  
package, a maximum 0.15mm pull back (L1) maybe present. L  
minus L1 to be equal to or greater than 0.3mm.  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN9171.1  
16  

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