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ISL6262IRZ-T

更新时间： 2024-01-12 08:27:30
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关输出元件
页数 文件大小 规格书
27页 562K
描述
Two-Phase Core Regulator for IMVP-6 Mobile CPUs

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中文翻译

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ISL6262IRZ-T 技术参数

生命周期：Unknown零件包装代码：QFN
包装说明：HVQCCN,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.16其他特性：ALSO ADJUSTABLE OUTPUT FROM 0.75 TO 1.5V; PWM CONTROL TECHNIQUE ALSO POSSIBLE
模拟集成电路 - 其他类型：DUAL SWITCHING CONTROLLER控制模式：CURRENT-MODE
控制技术：HYSTERETIC CURRENT MODE最大输入电压：5.25 V
最小输入电压：4.75 V标称输入电压：5 V
JESD-30 代码：S-PQCC-N48JESD-609代码：e3
长度：7 mm湿度敏感等级：2
功能数量：1端子数量：48
最高工作温度：100 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1 mm表面贴装：YES
切换器配置：PHASE-SHIFT最大切换频率：500 kHz
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：7 mmBase Number Matches：1

ISL6262IRZ-T 数据手册

 浏览型号ISL6262IRZ-T的Datasheet PDF文件第21页浏览型号ISL6262IRZ-T的Datasheet PDF文件第22页浏览型号ISL6262IRZ-T的Datasheet PDF文件第23页浏览型号ISL6262IRZ-T的Datasheet PDF文件第24页浏览型号ISL6262IRZ-T的Datasheet PDF文件第25页浏览型号ISL6262IRZ-T的Datasheet PDF文件第26页 
ISL6262  
Quad Flat No-Lead Plastic Package (QFN)  
L48.7x7  
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE  
(COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C)  
Micro Lead Frame Plastic Package (MLFP)  
2X  
0.15  
C A  
MILLIMETERS  
D
A
SYMBOL  
MIN  
0.80  
-
NOMINAL  
0.90  
MAX  
1.00  
0.05  
NOTES  
D/2  
A
A1  
A3  
b
-
-
-
2X  
0.20 REF  
0.23  
-
N
0.15 C  
B
6
0.18  
4.15  
4.15  
0.30  
4.45  
4.45  
5, 8  
INDEX  
AREA  
1
2
3
E/2  
D
7.00 BSC  
4.30  
-
D2  
E
7, 8  
E
B
7.00 BSC  
4.30  
-
E2  
e
7, 8  
0.50 BSC  
-
-
TOP VIEW  
k
0.25  
0.30  
-
-
L
0.40  
0.50  
8
A
/ /  
0.10 C  
N
48  
2
C
0.08 C  
Nd  
Ne  
12  
3
12  
3
SEATING PLANE  
A3 A1  
SIDE VIEW  
Rev. 2 5/06  
NOTES:  
5
NX b  
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.  
2. N is the number of terminals.  
0.10 M C A B  
D2  
8
7
3. Nd and Ne refer to the number of terminals on each D and E.  
4. All dimensions are in millimeters. Angles are in degrees.  
NX k  
D2  
(DATUM B)  
(DATUM A)  
2
N
5. Dimension b applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
6. The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
7. Dimensions D2 and E2 are for the exposed pads which provide  
improved electrical and thermal performance.  
(Ne-1)Xe  
REF.  
E2  
8. Nominal dimensionsare provided toassistwith PCBLandPattern  
Design efforts, see Intersil Technical Brief TB389.  
6
8
7
E2/2  
INDEX  
AREA  
3
2
1
NX L  
N
e
8
(Nd-1)Xe  
REF.  
BOTTOM VIEW  
A1  
NX b  
5
SECTION "C-C"  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN9199.2  
May 15, 2006  
27  
1...24252627

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