Datasheet > ISL23325

ISL23325

更新时间： 2023-12-20 18:44:39

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
20页	1259K
描述
Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP?)

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数据手册

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ISL23325 数据手册

ISL23325

Block Diagram

RH0

RH1

LOGIC

SCL

SDA

POWER UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

LEVEL

SHIFTER

I/O

BLOCK

WR0

WR1

VOLATILE

AND

WIPER

CONTROL

CIRCUITRY

VOLATILE

AND

WIPER

CONTROL

CIRCUITRY

RW0

RL0

RW1

RL1

GND

Pin Configurations

Pin Descriptions

ISL23325

(14 LD TSSOP)

TOP VIEW

TSSOP

µTQFN

6, 15

SYMBOL

DESCRIPTION

GND

Ground pin

I C bus/logic supply. Range 1.2V to

5.5V

GND

LOGIC

13 RL0

12 RW0

11 RH0

LOGIC

SDA

Logic Pin - Serial bus data

input/open drain output

SCL

Logic Pin - Serial bus clock input

RH1

RW1

RL1

Logic Pin - Hardwire slave address

pin for I C serial bus.

Range: V

or GND

LOGIC

Logic Pin - Hardwire slave address

pin for I C serial bus.

Range: V

or GND

LOGIC

ISL23325

(16 LD µTQFN)

Logic Pin - Hardwire slave address

TOP VIEW

pin for I C serial bus.

Range: V

or GND

LOGIC

RL1

RW1

RH1

RH0

RW0

RL0

DCP1 “low” terminal

DCP1 wiper terminal

DCP1 “high” terminal

DCP0 “high” terminal

DCP0 wiper terminal

DCP0 “low” terminal

SDA

RW0

SCL

11 RH0

10 RH1

RW1

Analog power supply.

Range 1.7V to 5.5V

Not Connected

FN7870 Rev 1.00

Page 2 of 20

September 23, 2015

123 4 5 6 7...20

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